ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
RX port-specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | RESERVED | - | 0 | Reserved |
6 | IS_LINE_LEN_CHG | R | 0 | Video Line Length Interrupt Status A change in video line length has been detected. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
5 | IS_LINE_CNT_CHG | R | 0 | Video Line Count Interrupt Status A change in number of video lines per frame has been detected. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
4 | IS_BUFFER_ERR | R | 0 | Receiver Buffer Error Interrupt Status A Receive Buffer overflow has been detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
3 | RESERVED | - | 0 | Reserved |
2 | IS_FPD3_PAR_ERR | R | 0 | FPD-Link III Receiver Parity Error Interrupt Status A parity error on the FPD-Link III interface for the receive port has been detected. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
1 | IS_PORT_PASS | R | 0 | Port Valid Interrupt Status A change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
0 | IS_LOCK_STS | R | 0 | Lock Interrupt Status A change in lock status has been detected. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |