The DS90UB662-Q1 implements an I2C master that acts as a proxy master to regenerate I2C accesses originating from a remote serializer (DS90UB633A-Q1). By default, the I2C Master Enable bit (I2C_MASTER_EN) is set = 0 in register 0x02[5] to block Master access to local deserialilzer I2C from remote serializers. Set I2C_MASTER_EN] = 1 if the system requires the deserializer to act as proxy master for remote serializers on the local deserializer I2C bus. The proxy master is an I2C-compatible master capable of operating with Standard-mode, Fast-mode, or Fast-mode Plus I2C timing. It is also capable of arbitration with other masters, allowing multiple masters and slaves to exist on the I2C bus. A separate I2C proxy master is implemented for each Receive port. This allows independent operation for all sources to the I2C interface. Arbitration between multiple sources is handled automatically using I2C multi-master arbitration.