ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:6 | BIST_OUT_MODE | R/W | 0x0 | BIST Output Mode 00 : No toggling 01 : Alternating 1/0 toggling 1x : Toggle based on BIST data |
| 5:4 | RESERVED | - | 0x0 | Reserved |
| 3 | RESERVED | R/W | 1 | Bist Configuration 1: Reserved 0: Bist configured through bits 2:0 in this register |
| 2:1 | BIST_CLOCK_SOURCE | R/W | 0 | BIST Clock Source This register field selects the BIST Clock Source at the Serializer. These register bits are automatically written to the CLOCK SOURCE bits (register offset 0x14) in the Serializer after BIST is enabled. See the appropriate Serializer register descriptions for details. |
| 0 | BIST_EN | R/W | 0 | BIST Control 1: Enabled 0: Disabled |