The SCL Low Time register field configures the low pulse width of the SCL output when the serializer is the master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional control channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and Low Time registers.