ZHCSEW6G may   2013  – november 2020 DS90UB913A-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Revision History
  6.   Device Comparison Table
  7. 5Pin Configuration and Functions
    1.     Pin Functions: DS90UB913A-Q1 Serializer
  8. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Timing Diagrams
    10. 6.10 Serializer Switching Characteristics
    11. 6.11 Typical Characteristics
  9. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB913A/914A
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS VDDIO Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
      2. 7.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 ID[x] Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  10.   Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  11.   Power Supply Recommendations
  12. 8Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Interconnect Guidelines
    2. 8.2 Layout Example
  13. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

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6.7 AC Timing Specifications (SCL, SDA) - I2C-Compatible

Over recommended supply and temperature ranges unless otherwise specified. (Figure 6-1)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCLSCL Clock FrequencyStandard Mode100kHz
Fast Mode400kHz
tLOWSCL Low PeriodStandard Mode4.7µs
Fast Mode1.3µs
tHIGHSCL High PeriodStandard Mode4.0µs
Fast Mode0.6µs
tHD:STAHold time for a start or a repeated start conditionStandard Mode4.0µs
Fast Mode0.6µs
tSU:STASet Up time for a start or a repeated start conditionStandard Mode4.7µs
Fast Mode0.6µs
tHD:DATData Hold TimeStandard Mode03.45µs
Fast Mode0900ns
tSU:DATData Set Up TimeStandard Mode250ns
Fast Mode100ns
tSU:STOSet Up Time for STOP ConditionStandard Mode4.0µs
Fast Mode0.6µs
tBUFBus Free time between Stop and StartStandard Mode4.7µs
Fast Mode1.3µs
trSCL & SDA Rise TimeStandard Mode1000ns
Fast Mode300ns
tfSCL & SDA Fall TimeStandard Mode300ns
Fast Mode300ns
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