米6体育平台手机版

ZHCSEW6G may 2013 – november 2020 DS90UB913A-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RTV|32
- MPQF166B

散热焊盘机械数据 (封装 | 引脚)

RTV|32
- QFND448B

订购信息

6.10 Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS		MIN	NOM	MAX	UNIT
t_LHT	CML Low-to-High Transition Time	R_L = 100 Ω (Figure 6-3)			150	330	ps
t_HLT	CML High-to-Low Transition Time	R_L = 100 Ω (Figure 6-3)			150	330	ps
t_DIS	Data Input Setup to PCLK	Serializer Data Inputs (Figure 6-8)		2			ns
t_DIH	Data Input Hold from PCLK	Serializer Data Inputs (Figure 6-8)		2			ns
t_PLD	Serializer PLL Lock Time⁽¹⁾⁽²⁾	R_L = 100 Ω (Figure 6-9)			1	2	ms
t_SD	Serializer Delay⁽²⁾	R_T = 100 Ω, 10–bit mode Register 0x03h b[0] (TRFB = 1) (Figure 6-10)		32.5T	38T	44T
t_SD	Serializer Delay⁽²⁾	R_T = 100 Ω, 12–bit mode Register 0x03h b[0] (TRFB = 1) (Figure 6-10)		11.75T	13T	15T
t_JIND	Serializer Output Deterministic Jitter ⁽³⁾⁽⁴⁾⁽⁵⁾	PRBS-7 test pattern, CDR PLL Loop BW = ƒ/15, BER = 1E-10	DOUT±		0.17	0.26	UI
t_JINR	Serializer Output Random Jitter ⁽³⁾⁽⁴⁾⁽⁵⁾	PRBS-7 test pattern, CDR PLL Loop BW = ƒ/15, BER = 1E-10	DOUT±		0.016		UI
t_JINT	Peak-to-Peak Serializer Output Total Jitter ⁽³⁾⁽⁵⁾⁽⁷⁾	PRBS-7 test pattern, CDR PLL Loop BW = ƒ/15, BER = 1E-10	DOUT±		0.4	0.52	UI
λ_STXBW	Serializer Jitter Transfer Function -3 dB Bandwidth	10–bit mode PCLK = 100 MHz. Default Registers			2.20		MHz
		12–bit high frequency mode PCLK = 75 MHz. Default Registers			2.20
		12–bit low frequency mode PCLK = 50 MHz. Default Registers			2.20
δ_STX	Serializer Jitter Transfer Function (Peaking)	10–bit mode PCLK = 100 MHz. Default Registers			1.06		dB
		12–bit high frequency mode PCLK = 75 MHz. Default Registers			1.09
		12–bit low frequency mode PCLK = 50 MHz. Default Registers			1.16
δ_STXf	Serializer Jitter Transfer Function (Peaking Frequency)	10–bit mode PCLK = 100 MHz. Default Registers			400		kHz
		12–bit high frequency mode PCLK = 75 MHz. Default Registers			500
		12–bit low frequency mode PCLK = 50 MHz. Default Registers			600

(1) t_PLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.

(2) Specification is verified by design.

(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, T_A = 25°C, and at the Recommended Operation Conditions at the time of product characterization and are not verified.

(4) Specification is verified by characterization and is not tested in production.

(5) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 x 28 )
12-bit HF mode: 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 )
12-bit LF mode: 1 UI = 1 / ( PCLK_Freq. x 28 )

(6) To ensure optimum device functionality, It is recommended to NOT write to any RESERVED registers.

(7) Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input.