ZHCSEW6G may   2013  – november 2020 DS90UB913A-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Revision History
  6.   Device Comparison Table
  7. 5Pin Configuration and Functions
    1.     Pin Functions: DS90UB913A-Q1 Serializer
  8. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Timing Diagrams
    10. 6.10 Serializer Switching Characteristics
    11. 6.11 Typical Characteristics
  9. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB913A/914A
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS VDDIO Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
      2. 7.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 ID[x] Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  10.   Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  11.   Power Supply Recommendations
  12. 8Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Interconnect Guidelines
    2. 8.2 Layout Example
  13. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics(1)(2)(3)

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
LVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIHHigh Level Input VoltageVIN = 3 V to 3.6 V2VINV
VILLow Level Input VoltageVIN = 3 V to 3.6 VGND0.8V
IINInput CurrentVIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V–20±120µA
VOHHigh Level Output VoltageVDDIO = 3 V to 3.6 V, IOH = −4 mA2.4VDDIOV
VOLLow Level Output VoltageVDDIO = 3 V to 3.6 V, IOL = 4 mAGND0.4V
IOSOutput Short Circuit CurrentVOUT = 0 VSerializer
GPO Outputs		–15mA
IOZTRI-STATE Output CurrentPDB = 0 V,
VOUT = 0 V or VDDIO		Serializer
GPO Outputs		–2020µA
CGPOPin CapacitanceGPO [3:0]1.5pF
LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIHHigh Level Input VoltageVIN = 1.71 V to 1.89 V0.65 VINVINV
VILLow Level Input VoltageVIN = 1.71 V to 1.89 VGND0.35 VIN
IINInput CurrentVIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V–20±120µA
VOHHigh Level Output VoltageVDDIO = 1.71 V to 1.89 V, IOH = −4 mAVDDIO - 0.45VDDIOV
VOLLow Level Output VoltageVDDIO = 1.71 V to 1.89 V IOL = 4 mAGND0.45V
IOSOutput Short Circuit CurrentVOUT = 0 VSerializer
GPO Outputs		–11mA
IOZTRI-STATE Output CurrentPDB = 0 V,
VOUT = 0 V or VDDIO		Serializer
GPO Outputs		-2020µA
CGPOPin CapacitanceGPO [3:0]1.5pF
IIN-STRAPStrap pin input currentVIN = 0 V to VDD_n-11µA
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIHHigh Level Input VoltageVIN = 2.52 V to 3.08 V0.7 VINVINV
VILLow Level Input VoltageVIN = 2.52 V to 3.08 VGND0.3 VIN
IINInput CurrentVIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V–20±120µA
VOHHigh Level Output VoltageVDDIO = 2.52 V to 3.08 V, IOH = −4 mAVDDIO - 0.4VDDIOV
VOLLow Level Output VoltageVDDIO =2.52 V to 3.08V IOL = 4 mAGND0.4V
IOSOutput Short Circuit CurrentVOUT = 0 VSerializer
GPO Outputs		–11mA
IOZTRI-STATE Output CurrentPDB = 0 V,
VOUT = 0 V or VDDIO		Serializer
GPO Outputs		–2020µA
CGPOPin CapacitanceGPO [3:0]1.5pF
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
VODDifferential Output VoltageRL = 100 Ω (Figure 6-6), Back Channel Disabled640824mV
VOUTSingle-Ended Output VoltageRL = 50 Ω (Figure 6-6), Back Channel Disabled320412
ΔVODDifferential Output
Voltage Unbalance		RL = 100 Ω150mV
VOSOutput Offset VoltageRL = 100 Ω (Figure 6-6)VDD_n - VOD/2V
ΔVOSOffset Voltage UnbalanceRL = 100 Ω150mV
IOSOutput Short Circuit CurrentDOUT+ = 0 V or DOUT– = 0 V–26mA
RTDifferential Internal Termination ResistanceDifferential across DOUT+ and DOUT–80100120Ω
Single-ended
Termination Resistance		DOUT+ or DOUT–405060
VID-BCBack Channel Differential Input VoltageBack Channel Frequency = 5.5 MHz(10)260mV
VIN-BCBack Channel Single-Ended Input Voltage130mV
SERIALIZER SUPPLY CURRENT
IDDTSerializer (Tx)
VDD_n Supply Current (includes load current)		RL = 100 Ω
WORST CASE pattern
(Figure 6-2)		VDD_n = 1.89 V VDDIO = 3.6 V
f = 100 MHz, 10-bit mode
Default Registers		6180mA
VDD_n = 1.89 V VDDIO = 3.6 V
f = 75 MHz, 12-bit high frequency mode
Default Registers		6180mA
VDD_n = 1.89 V VDDIO = 3.6 V
f = 50 MHz, 12-bit low frequency mode
Default Registers		6180
IDDTSerializer (Tx)
VDD_n Supply Current (includes load current)		RL = 100 Ω
RANDOM PRBS-7 pattern		VDD_n = 1.89 V VDDIO = 3.6 V
f = 100 MHz, 10-bit mode
Default Registers		65mA
VDD_n = 1.89 V VDDIO = 3.6 V
f = 75 MHz, 12-bit high frequency mode
Default Registers		64
VDD_n = 1.89 V VDDIO = 3.6 V
f = 50 MHz, 12-bit low frequency mode
Default Registers		63
IDDIOTSerializer (Tx)
VDDIO Supply Current (includes load current)		RL = 100 Ω
WORST CASE pattern
(Figure 6-2)		VDDIO = 1.89 V
f = 75 MHz, 12-bit high frequency mode
Default Registers		1.53mA
VDDIO = 3.6 V
f = 75 MHz, 12-bit high frequency
mode Default Registers		58
IDDTZSerializer (Tx) Supply Current Power DownPDB = 0V; All other LVCMOS Inputs = 0 VVDDIO=1.89 V
Default Registers		3001000µA
VDDIO = 3.6 V
Default Registers		3001000µA
IDDIOTZSerializer (Tx) VDDIO Supply Current Power DownPDB = 0V; All other LVCMOS Inputs = 0 VVDDIO = 1.89 V
Default Registers		15100µA
VDDIO = 3.6 V
Default Registers		15100µA
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