The DS90UB913A-Q1 device divides the clock internally by divide-by-1 in the 12-bit low frequency mode, by divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, the DS90UB914A-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to calculate the maximum line rate in the different modes:

• For the 12-bit low frequency mode, Line rate = f_PCLK*28; for example, f_PCLK = 50 MHz, line rate = 50*28 = 1.4 Gbps
• For the 12-bit high frequency mode, Line rate = f_PCLK*(2/3)*28; for example, f_PCLK = 75 MHz, line rate = (75)*(2/3)*28 = 1.4 Gbps
• For the 10-bit mode, Line rate = f_PCLK/2*28; for example, f_PCLK = 100 MHz, line rate = (100/2)*28 = 1.4 Gbps