7.3.1 High-Speed Forward Channel Data Transfer

The high-speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, I²C, and I2S audio transmitted from serializer to deserializer. Figure 19 shows the serial stream PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, DC-balanced and scrambled.

Figure 19. FPD-Link III Serial Stream

The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 96 MHz (LFMODE=0). This corresponds to an application payload rate range of 155 Mbps to 2.976 Gbps, with an actual line rate range of 525 Mbps to 3.36 Gbps.

7.3.2 Low-Speed Back Channel Data Transfer

The low-speed back channel of the DS90UB924-Q1 provides bidirectional communication between the display and host processor. The back channel control data is transferred over the single serial link along with the high-speed forward data, DC balance coding, and embedded clock information. Together, the forward channel and back channel form the bidirectional control channel (BCC). This architecture provides a backward path across the serial link together with a high speed forward channel. The back channel contains the I²C, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.

7.3.3 Backward Compatible Mode

The DS90UB924-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q for PCLK frequencies ranging from 15 MHz to 65 MHz. The deserializer receives 28 bits of data over a single serial FPD-Link III pair operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to a line rate of 140 Mbps to 2.1 Gbps. The backward compatibility configuration can be selected through the MODE_SEL pin or programmed through the device control registers (Table 8). The bidirectional control channel, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode. However, local I²C access to the serializer is still available.

7.3.4 Input Equalization

An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces medium-induced deterministic jitter.

The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 6). This mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value stored in the control registers (Table 8).

7.3.5 Common Mode Filter Pin (CMF)

The deserializer provides access to the center tap of the internal CML termination. A 0.1 μF capacitor must be connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 37). This increases noise rejection capability in high-noise environments.

7.3.6 Power Down (PDB)

The deserializer has a PDB input pin to enable or power down the device. This pin may be controlled by an external device, or through V_DDIO, where V_DDIO = 3 V to 3.6 V or V_DD33. To save power, disable the link when the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before V_DD33 and V_DDIO have reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before releasing or driving high (See Recommended Operating Conditions ). If the PDB is pulled up to V_DDIO = 3.0 V to 3.6 V or V_DD33 directly, a 10 kΩ pullup resistor and a >10 µF capacitor to ground are required (See Figure 37).

Toggling PDB low POWER DOWN the device and RESET all control registers to default. During this time, PDB must be held low for a minimum of 2 ms (see AC Electrical Characteristics).

7.3.7 Video Control Signals

The video control signal bits embedded in the high-speed FPD-Link (OpenLDI) LVDS are subject to certain limitations relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width filter on these signals to help eliminate spurious transitions.

Normal Mode Control Signals (VS, HS, DE) have the following restrictions:

• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 8. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 8. DE can have at most two transitions per 130 PCLKs.

7.3.8 EMI Reduction Features

7.3.9 Built In Self Test (BIST)

An optional At-speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and the low-speed back channel without external data connections. This is useful in the prototype stage, equipment production, in-system test, and system diagnostics.

7.3.9.1 BIST Configuration and Status

The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may select either an external PCLK or the 33 MHz internal oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration register.

When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame.

The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.

See Figure 20 for the BIST mode flow diagram.

7.3.9.1.1 Sample BIST Sequence

1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer goes high, and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.
3. To stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test result is held on the PASS pin. If the test ran error free, the PASS output remains HIGH. If there one or more errors were detected, the PASS output outputs constant LOW. The PASS output state is held until a new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may be of any length.

The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so forth.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal condition enhancements (Rx equalization).

Figure 20. BIST Mode Flow Diagram

7.3.9.2 Forward Channel and Back Channel Error Checking

The deserializer, on locking to the serial stream, compares the recovered serial stream with all zeroes and records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer. Forward channel errors may also be read from register 0x25 ( Table 8).

The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream, as indicated by link detect status (register bit 0x1C[0] - Table 8). CRC errors are recorded in an 8-bit register in the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or the serializer enters BIST mode again.

Figure 21. BIST Waveforms

7.3.10 Internal Pattern Generation

The DS90UB924-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern is displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to TI Application Note: (AN-2198).

7.3.11 Serial Link Fault Detect

The DS90UB924-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x1C (Table 8). The device detects any of the following conditions:

1. Cable open
2. RIN+ to - short
3. RIN+ to GND short
4. RIN- to GND short
5. RIN+ to battery short
6. RIN- to battery short
7. Cable is linked incorrectly (RIN+/RIN- connections reversed)

7.3.12 Oscillator Output

The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost. This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable) Table 8.

7.3.13 Interrupt Pin (INTB / INTB_IN)

1. Read HDCP_ISR Register 0xC7. (Table 8)
2. On the serializer, set register (ICR) 0xC6[5] = 1 and 0xC6[0] = 1 to configure the interrupt.
3. On the serializer, read from ISR register 0xC7 to arm the interrupt for the first time.
4. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
5. The external controller detects INTB = LOW and reads the ISR register to determine the interrupt source. Reading this register also clears and resets the interrupt.

The INTB_IN signal is sampled and required approximately 8.6 μs of the minimum setup and hold time.

8.6 μs = 30 bit per back channel frame / (5 Mbps rate × ±30% Variation) = 30 / (5E6 × 0.7)

Note that -30% is the worst case.

7.3.14 General-Purpose I/O

7.3.15 I2S Audio Interface

The DS90UB924-Q1 deserializer features six I2S output pins that, when paired with a DS90UB927Q-Q1 serializer, supports surround-sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1 MHz and the smaller of < PCLK/4 or < 13 MHz. Four I2S data outputs carry two channels of I2S-formatted digital audio each, with each channel delineated by the word select (I2C_WC) input. The I2S audio interface is not available in Backwards Compatibility Mode (BKWD = 1).

Figure 22. I2S Connection Diagram

Figure 23. I2S Frame Timing Diagram

When paired with a DS90UB921-Q1 or DS90UB925Q-Q1, the DS90UB924-Q1 I2S interface supports a single I2S data output through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-bit video mode).

7.3.16 AV Mute Prevention

The DS90UB924-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE state, the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE Register 0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This will ensure AV MUTE mode is not entered during normal operation

If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of the paired Serializer. This setting is not accessible from DS90UB924-Q1.

7.3.17 OEN Toggling Limitation

OEN must be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN function is asynchronous signal to internal digital blocks, repeatedly OEN toggling may result in horizontal pixel shift at the LVDS output. To avoid this, recommend to reset by programming Register 0x01[0] for digital blocks after OEN turns to ON state.

7.4.1 Clock and Output Status

When PDB is driven HIGH, the CDR PLL begins locking to the serial input, and LOCK is TRI-STATE or LOW (depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the LVCMOS and LVDS outputs. The state of the outputs is based on the OEN and OSS_SEL setting (Table 5) or register bit (Table 8).

7.4.2 FPD-Link (OpenLDI) Input Frame and Color Bit Mapping Select

The DS90UB924-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different mapping schemes, shown in Figure 24, or MSBs on TxOUT[3], shown in Figure 25. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 8).

Figure 24. 24-bit Color FPD-Link (OpenLDI) Mapping: LSBs on TxOUT3 (MAPSEL=L)

Figure 25. 24-bit Color FPD-Link (OpenLDI) Mapping: MSBs on TxOUT3 (MAPSEL=H)

Figure 26. 18-bit Color FPD-Link (OpenLDI) Mapping (MAPSEL = L)

Figure 27. 18-bit Color FPD-Link (OpenLDI) Mapping (MAPSEL = H)

7.4.3 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (Table 8) or by the LFMODE Pin. This mode optimizes device operation for lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the TxCLKOUT± PCLK frequency is between 15 MHz and 96 MHz. If LFMODE is High (LFMODE=1), the TxCLKOUT± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by four. Thus, for the operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective data payload of 175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative to the input data rate remains the same.

7.4.4 Mode Select (MODE_SEL)

Device configuration may be done via the MODE_SEL pin or via register (Table 7). A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and V_DD33 to select one of the 9 possible selected modes. See Figure 28 and Table 6.

Figure 28. MODE_SEL Connection Diagram

7.4.5 Repeater Configuration

The supported Repeater application provides a mechanism to extend transmission over multiple links to multiple display devices.

For the repeater application, this document refers to the DS90UB927Q-Q1 as the Transmitter (TX), and refers to the DS90UB924-Q1 as the Receiver (RX). Figure 29 shows the maximum configuration supported for Repeater implementations. Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.

Figure 29. Maximum Repeater Application

In a repeater application, the I²C interface at each TX and RX is configured to transparently pass I²C communications upstream or downstream to any I²C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

Figure 30. 1:2 Repeater Configuration

7.4.5.1 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter (Figure 31).

1. Video Data – Connect all FPD-Link (OpenLDI) data and clock pairs
2. I²C – Connect SCL and SDA signals. Both signals must be pulled up to V_DD33 or V_DDIO = 3.0 V to 3.6 V with 4.7-kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I²C address.
5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UB924-Q1 INTB_IN pin to the serializer INTB pin. The signal must be pulled up to V_DDIO with a 10-kΩ resistor.

Figure 31. Repeater Connection Diagram

7.4.5.1.1 Repeater Fan-Out Electrical Requirements

Repeater applications requiring fan-out from one DS90UB924-Q1 deserializer to up to three DS90UB927Q-Q1 serializers requires special considerations for routing and termination of the FPD-Link (OpenLDI) differential traces. Figure 32 Details the requirements that must be met for each signal pair:

Figure 32. FPD-Link (OpenLDI) Fan-Out Electrical Requirements

Table 7. Serial Control Bus Addresses for IDx

Table 8. Serial Control Bus Registers ^{(1) (2)}