ZHCSDA1D July   2012  – August 2017 DS90UB926Q-Q1

PRODUCTION DATA.  

1. 1 特性
2. 2 应用范围
3. 3 说明
4. 4 修订历史记录
5. 5 说明 （续）
6. 6 Pin Configuration and Functions
7. 7 Specifications
   1. 7.1  Absolute Maximum Ratings
   2. 7.2  ESD Ratings
   3. 7.3  Recommended Operating Conditions
   4. 7.4  Thermal Information
   5. 7.5  DC Electrical Characteristics
   6. 7.6  AC Electrical Characteristics
   7. 7.7  DC and AC Serial Control Bus Characteristics
   8. 7.8  Timing Requirements
   9. 7.9  Timing Requirements for the Serial Control Bus
   10. 7.10 Switching Characteristics
   11. 7.11 Timing Diagrams
   12. 7.12 Typical Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1  High-Speed Forward Channel Data Transfer
      2. 8.3.2  Low-Speed Back Channel Data Transfer
      3. 8.3.3  Backward-Compatible Mode
      4. 8.3.4  Input Equalization Gain
      5. 8.3.5  Common-Mode Filter Pin (CMF)
      6. 8.3.6  Video Control Signal Filter
      7. 8.3.7  EMI Reduction Features
         1. 8.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 8.3.8  Enhanced Progressive Turnon (EPTO)
      9. 8.3.9  LVCMOS VDDIO Option
      10. 8.3.10 Power Down (PDB)
      11. 8.3.11 Stop Stream Sleep
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Oscillator Output
      14. 8.3.14 Pixel Clock Edge Select (RFB)
      15. 8.3.15 Image Enhancement Features
          1. 8.3.15.1 White Balance
             1. 8.3.15.1.1 LUT Contents
             2. 8.3.15.1.2 Enabling White Balance
          2. 8.3.15.2 Adaptive HI-FRC Dithering
      16. 8.3.16 Internal Pattern Generation
      17. 8.3.17 Built-In Self Test (BIST)
          1. 8.3.17.1 BIST Configuration and Status
             1. 8.3.17.1.1 Sample BIST Sequence
          2. 8.3.17.2 Forward Channel And Back Channel Error Checking
      18. 8.3.18 I2S Receiving
          1. 8.3.18.1 I2S Jitter Cleaning
          2. 8.3.18.2 Secondary I2S Channel
             1. 8.3.18.2.1 MCLK
      19. 8.3.19 Interrupt Pin — Functional Description and Usage (INTB)
      20. 8.3.20 GPIO[3:0] and GPO_REG[8:4]
          1. 8.3.20.1 GPO_REG[8:4] Enable Sequence
   4. 8.4 Device Functional Modes
      1. 8.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      2. 8.4.2 Low Frequency Optimization (LFMODE)
      3. 8.4.3 Configuration Select (MODE_SEL)
      4. 8.4.4 Repeater Application
         1. 8.4.4.1 Repeater Connections
   5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
   6. 8.6 Register Maps
9. 9 Application and Implementation
   1. 9.1 Application Information
      1. 9.1.1 Display Application
   2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
         1. 9.2.2.1 Transmission Media
      3. 9.2.3 Application Curves
10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
11. 11Layout
    1. 11.1 Layout Guidelines
       1. 11.1.1 CML Interconnect Guidelines
    2. 11.2 Layout Examples
12. 12器件和文档支持
    1. 12.1 文档支持
       1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
13. 13机械、封装和可订购信息