ZHCSDB5B MARCH 2013 – January 2015 DS90UB928Q-Q1
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 应用图
- 5 修订历史记录
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 DC Electrical Characteristics
- 7.6 AC Electrical Characteristics
- 7.7 Timing Requirements for the Serial Control Bus
- 7.8 Timing Requirements
- 7.9 DC and AC Serial Control Bus Characteristics
- 7.10 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 High Speed Forward Channel Data Transfer
- 8.3.2 Low Speed Back Channel Data Transfer
- 8.3.3 Backward Compatible Mode
- 8.3.4 Input Equalization
- 8.3.5 Common Mode Filter Pin (CMF)
- 8.3.6 Power Down (PDB)
- 8.3.7 Video Control Signals
- 8.3.8 EMI Reduction Features
- 8.3.9 Built In Self Test (BIST)
- 8.3.10 Internal Pattern Generation
- 8.3.11 Image Enhancement Features
- 8.3.12 Serial Link Fault Detect
- 8.3.13 Oscillator Output
- 8.3.14 Interrupt Pin (INTB)
- 8.3.15 General-Purpose I/O
- 8.3.16 I2S Audio Interface
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械封装和可订购信息
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90UB928Q-Q1 deserializer, in conjunction with a DS90UB925Q-Q1 or DS90UB927Q-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. It converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (FPD-Link), and I2S audio data. The serial bus scheme, FPD-Link III, supports high speed forward channel data transmission and low speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
9.2 Typical Application
Figure 41 shows a typical application of the DS90UB928Q-Q1 deserializer for an 85 MHz 24-bit Color Display Application. Inputs utilize 0.1-µF coupling capacitors to the line and the deserializer provides internal termination. The voltage rating of the coupling capacitors should be ≥50 V and should use a small body capacitor size, such as 0402 or 0602, to help ensure good signal integrity. The FPD-Link LVDS differential outputs require 100-Ω termination resistors at the receiving device or display.
Bypass capacitors must be placed near the power supply pins. At a minimum, three 4.7-μF capacitors, one placed at each power supply pin, are required for local device bypassing. If additional bypass capacitors are used, place the smaller value components closer to the pin. Ferrite beads are required on the two supplies (VDD33 and VDDIO) for effective noise suppression. Pins VDD33_A and VDD33_B should be connected directly to ensure ESD performance. The interface to the display is FPD-Link LVDS. The VDDIO pin may be connected to 3.3 V or 1.8 V. A delay capacitor (>10 µF) and pullup resistor (10 kΩ) should be placed on the PDB signal to delay the enabling of the device until power is stable.
Figure 41. Typical Connection Diagram
Figure 42. Typical Display System Diagram
9.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 8. Design Parameters
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VDDIO | 1.8 V or 3.3 V |
| VDD33 | 3.3 V |
| AC Coupling Capacitor for RIN± | 100 nF |
| PCLK Frequency | 78 MHz |
9.2.2 Detailed Design Procedure
9.2.2.1 Transmission Media
The DS90UB927Q-Q1 and DS90UB928Q-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define the acceptable data eye opening width and eye opening height. A differential probe should be used to measure across the termination resistor at the CMLOUT± pin Figure 2.
9.2.2.2 Display Application
The DS90UB928Q-Q1, in conjunction with the DS90UB925Q-Q1 or DS90UB927Q-Q1, is intended for interfacing with a host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three control bits (VS, HS and DE) and four I2S audio streams.
9.2.3 Application Curves
Figure 43. 78-MHz Clock at Serializer and Deserializer
Figure 44. CMLOUT of Deserializer from 48-MHz Input Clock