10.1 Layout Guidelines

Circuit board layout and stack-up for the FPD-Link III devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pick-up, feedback, and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Ceramic capacitors may be in the 2.2 µF to 10 µF range. The voltage rating of the ceramic capacitors must be at least 5× higher than the power supply voltage being used.

TI recommends surface-mount capacitors due to their smaller parasitics. When using multiple capacitors per supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50 µF to 100 µF range, which smooths low frequency switching noise. TI recommends that the user connect the power and ground pins directly to the power and ground planes, and place a via on both ends of the bypass capacitors connected to the plane. Connecting the power or ground pins to an external bypass capacitor can increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. The small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also common practice to use two vias from the power and ground pins to the planes to reduce the impedance at high frequency.

Place the LVCMOS signals away from the differential lines to prevent coupling between the LVCMOS and differential lines. A differential impedance of 100 Ω is typically recommended for STP interconnect, and a single-ended impedance of 50 Ω is recommended for coaxial interconnects. The closely coupled lines help to ensure that coupled noise appears as common-mode, and thus is rejected by the receivers. The tightly coupled lines also radiate less.

Information on the WQFN package is provided in AN-1187 Leadless leadframe package (LLP) (SNOA401).