7.3.11.2 Adaptive Equalizer Algorithm

The AEQ process steps through the allowed values of the equalizer controls to find a value that allows the Clock Data Recovery (CDR) circuit to maintain a valid lock condition. For each EQ setting, the circuit waits for a programmed relock time period, then checks the results for a valid lock. If a valid lock is detected, the circuit will stop at the current EQ setting and maintain a constant value for as long as the lock state persists. If the deserializer loses the lock, the adaptive equalizer will resume the LOCK algorithm and the EQ setting is incremented to the next valid state. When the lock is lost, the circuit will continue searching the EQ settings to find a valid setting to reacquire the serial data stream sent by the serializer that remains locked.