The DS90UB954-Q1 has seven GPIO pins that can output data received from the forward channel when paired with the DS90UB935-Q1 or DS90UB953-Q1 serializer. The remote Serializer GPIO are mapped to GPIO. Each GPIO pin can be programmed for output mode and mapped. Up to four GPIOs are supported in the forward direction on each FPD-Link III Receive port (see Table 7-99). Each forward channel GPIO (from any port) can be mapped to any GPIO output pin. The DS90UB933-Q1 and DS90UB913A-Q1 GPIOs cannot be configured as inputs for remote communication over the forward channel to the DS90UB954-Q1.

The timing for the forward channel GPIO is dependant on the number of GPIOs assigned at the serializer. When a single GPIO input from the DS90UB953-Q1 or DS90UB935-Q1 serializer is linked to a DS90UB954-Q1 deserializer, the GPIO output value is sampled every forward channel transmit frame. Two linked GPIO are sampled every two forward channel frames and three or four linked GPIO are sampled every five frames. The typical minimum latency for the GPIO remains consistent (approximately 225 ns), but as the information gets spread over multiple frames, the jitter is typically increased on the order of the sampling period (number of forward channel frames). TI recommends maintaining a 4x oversampling ratio for linked GPIO throughput. For example, when operating in 4-Gbps synchronous mode with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the number of GPIO linked over the forward channel is shown in #GUID-1F4E3DB6-F592-4740-B4D9-66BF23083B39/X3483.

In addition to mapping remote serializer GPI, an internally generated FrameSync (see GUID-DADE79CE-A2B9-46FA-81B2-84BAB7298C4D.html#GUID-DADE79CE-A2B9-46FA-81B2-84BAB7298C4D) or other control signals may be output from any of the deserializer GPIOs for synchronization with a local processor or another deserializer.