ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | RESERVED | R | 0x0 | Reserved |
| 6:4 | AEQ_ERR_CTL | R/W | 0x7 | AEQ Error Control Setting any bits in AEQ_ERR_CTL will enable FPD3 error checking during the Adaptive Equalization process. Errors are accumulated over 1/2 of the period of the timer set by the ADAPTIVE_EQ_RELOCK_TIME filed in the AEQ_CTL2 register. If the number of errors is greater than the programmed threshold (AEQ_ERR_THOLD), the AEQ will attempt to increase the EQ setting. The errors may also be checked as part of EQ setting validation if AEQ_2STEP_EN is set. The following errors are checked based on this three bit field: [6] FPD-Link III clock errors [5] Packet encoding errors [4] Parity errors |
| 3 | RESERVED | R/W | 0x0 | Reserved |
| 2 | AEQ_2STEP_EN | R/W | 0x0 | AEQ 2-step enable This bit enables a two-step operation as part of the Adaptive EQ algorithm. If disabled, the state machine will wait for a programmed period of time, then check status to determine if setting is valid. If enabled, the state machine will wait for 1/2 the programmed period, then check for errors over an additional 1/2 the programmed period. If errors occur during the 2nd step, the state machine will immediately move to the next setting. 0 : Wait for full programmed delay, then check instantaneous lock value 1 : Wait for 1/2 programmed time, then check for errors over 1/2 programmed time. The programmed time is controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_CTL2 register |
| 1 | AEQ_OUTER_LOOP | R/W | 0x0 | AEQ outer loop control This bit controls whether the Equalizer or SFILTER adaption is the outer loop when the AEQ adaption includes SFILTER adaption. 0 : AEQ is inner loop, SFILTER is outer loop 1 : AEQ is outer loop, SFILTER is inner loop |
| 0 | AEQ_SFILTER_EN | R/W | 0x1 | Enable SFILTER Adaption with AEQ Setting this bit allows SFILTER adaption as part of the Adaptive Equalizer algorithm. |