ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | RESERVED | R | 0x0 | Reserved |
| 6 | CSI_CAL_EN | R/W | 0x0 | Enable initial CSI Skew-Calibration sequence When the initial skew-calibration sequence is enabled, the CSI Transmitter will send the sequence at initialization, prior to sending any HS data. This bit should be set when operating at 1.6 Gbps CSI speed (as configured in the CSI_PLL_CTL register). 0: Disabled 1: Enabled |
| 5:4 | CSI_LANE_COUNT | R/W | 0x0 | CSI lane count 00: 4 lanes 01: 3 lanes 10: 2 lanes 11: 1 lane If CSI_REPLICATE is set in the FWD_CTL2 register, the device must be programmed for 1 or 2 lanes only. |
| 3:2 | CSI_ULP | R/W | 0x0 | Force LP00 state on data/clock lanes 00: Normal operation 01: LP00 state forced only on data lanes 10: Reserved 11: LP00 state forced on data and clock lanes |
| 1 | CSI_CONTS _CLOCK | R/W | 0x0 | Enable CSI continuous clock mode. CSI-2 Tx outputs will provide a continuous clock output signal once first packet is received. 0: Disabled 1: Enabled |
| 0 | CSI_ENABLE | R/W | 0x0 | Enable CSI output 0: Disabled 1: Enabled |