ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
RX port specific register. The FPD-Link III Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | I2C_PASS _THROUGH_ALL | R/W | 0x0 | I2C Pass-Through All Transactions 0: Disabled 1: Enabled |
| 6 | I2C_PASS _THROUGH | R/W | 0x0 | I2C Pass-Through to Serializer if decode matches 0: Pass-Through Disabled 1: Pass-Through Enabled |
| 5 | AUTO_ACK_ALL | R/W | 0x0 | Automatically Acknowledge all I2C writes independent of the forward channel lock state or status of the remote Acknowledge 1: Enable 0: Disable |
| 4 | BC_ALWAYS_ON | R/W | 0x1 | Back channel enable 1: Back channel is always enabled independent of I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL 0: Back channel enable requires setting of either I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL This bit may only be written through a local I2C controller. |
| 3 | BC_CRC _GENERATOR _ENABLE | R/W | 0x1 | Back Channel CRC Generator Enable 0: Disable 1: Enable |
| 2:0 | BC_FREQ_SELECT | R/W | S | Back Channel Frequency Select. Default value set by strap condition upon
asserting PDB = HIGH. 000: 2.5 Mbps (select for DS90UB933-Q1 or DS90UB913A-Q1 compatibility) 001- 011: Reserved 010: 10 Mbps (select for non-synchronous back channel compatibility) 101: 25 Mbps 110: 50 Mbps (default for DS90UB953-Q1 or DS90UB935-Q1 CSI Synchronous back channel compatibility) 111: Reserved Note that changing this setting will result in some errors on the back channel for a short period of time. If set over the control channel, the Serializer should first be programmed to Auto-Ack operation to avoid a control channel timeout due to lack of response from the Deserializer. |