ZHCSGT3C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | INTERRUPT_STS | R | 0x0 | Global Interrupt: Set if any enabled interrupt is indicated in the individual status bits in this register. The setting of this bit is not dependent on the INT_EN bit in the INTERRUPT_CTL register but does depend on the IE_xxx bits. For example, if IE_RX0 and IS_RX0 are both asserted, the INTERRUPT_STS bit is set to 1. |
| 6:5 | RESERVED | R | 0x0 | Reserved |
| 4 | IS_CSI_TX0 | R | 0x0 | CSI Transmit Port Interrupt: An interrupt has occurred for CSI Transmitter Port 0. This interrupt is cleared upon reading the CSI_TX_ISR register for CSI Transmit Port. |
| 3:2 | RESERVED | R | 0x0 | Reserved |
| 1 | IS_RX1 | R | 0x0 | RX Port 1 Interrupt: An interrupt has occurred for Receive Port 1. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
| 0 | IS_RX0 | R | 0x0 | RX Port 0 Interrupt: An interrupt has occurred for Receive Port 0. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |