ZHCSIG1D August   2016  – September 2023 DS90UB960-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  CSI-2 Timing Specifications
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Receiver Port Control
        1. 7.4.5.1 Video Stream Forwarding
      6. 7.4.6  Input Jitter Tolerance
      7. 7.4.7  Adaptive Equalizer
        1. 7.4.7.1 Transmission Distance
        2. 7.4.7.2 Channel Requirements
        3. 7.4.7.3 Adaptive Equalizer Algorithm
        4. 7.4.7.4 AEQ Settings
          1. 7.4.7.4.1 AEQ Start-Up and Initialization
          2. 7.4.7.4.2 AEQ Range
          3. 7.4.7.4.3 AEQ Timing
          4. 7.4.7.4.4 AEQ Threshold
      8. 7.4.8  Channel Monitor Loop-Through Output Driver
        1. 7.4.8.1 Code Example for CMLOUT FPD3 RX Port 0:
      9. 7.4.9  RX Port Status
        1. 7.4.9.1 RX Parity Status
        2. 7.4.9.2 FPD-Link Decoder Status
        3. 7.4.9.3 RX Port Input Signal Detection
        4. 7.4.9.4 Line Counter
        5. 7.4.9.5 Line Length
      10. 7.4.10 Sensor Status
      11. 7.4.11 GPIO Support
        1. 7.4.11.1 GPIO Input Control and Status
        2. 7.4.11.2 GPIO Output Pin Control
        3. 7.4.11.3 Forward Channel GPIO
        4. 7.4.11.4 Back Channel GPIO
        5. 7.4.11.5 GPIO Pin Status
        6. 7.4.11.6 Other GPIO Pin Controls
      12. 7.4.12 RAW Mode LV / FV Controls
      13. 7.4.13 CSI-2 Protocol Layer
      14. 7.4.14 CSI-2 Short Packet
      15. 7.4.15 CSI-2 Long Packet
      16. 7.4.16 CSI-2 Data Identifier
      17. 7.4.17 Virtual Channel and Context
      18. 7.4.18 CSI-2 Mode Virtual Channel Mapping
        1. 7.4.18.1 Example 1
        2. 7.4.18.2 Example 2:
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Output Bandwidth
        1. 7.4.20.1 CSI-2 Output Bandwidth Calculation Example
      21. 7.4.21 CSI-2 Transmitter Status
      22. 7.4.22 Video Buffers
      23. 7.4.23 CSI-2 Line Count and Line Length
      24. 7.4.24 FrameSync Operation
        1. 7.4.24.1 External FrameSync Control
        2. 7.4.24.2 Internally Generated FrameSync
          1. 7.4.24.2.1 Code Example for Internally Generated FrameSync
      25. 7.4.25 CSI-2 Forwarding
        1. 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.25.2 Synchronized CSI-2 Forwarding
        3. 7.4.25.3 Basic Synchronized CSI-2 Forwarding
          1. 7.4.25.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 7.4.25.4 Line-Interleaved CSI-2 Forwarding
          1. 7.4.25.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 7.4.25.5 Line-Concatenated CSI-2 Forwarding
          1. 7.4.25.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 7.4.25.6 CSI-2 Replicate Mode
        7. 7.4.25.7 CSI-2 Transmitter Output Control
        8. 7.4.25.8 Enabling and Disabling CSI-2 Transmitters
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus
      2. 7.5.2  Second I2C Port
      3. 7.5.3  I2C Target Operation
      4. 7.5.4  Remote Target Operation
      5. 7.5.5  Remote Target Addressing
      6. 7.5.6  Broadcast Write to Remote Devices
        1. 7.5.6.1 Code Example for Broadcast Write
      7. 7.5.7  I2C Controller Proxy
      8. 7.5.8  I2C Controller Proxy Timing
        1. 7.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 7.5.9  Interrupt Support
        1. 7.5.9.1 Code Example to Enable Interrupts
        2. 7.5.9.2 FPD-Link III Receive Port Interrupts
        3. 7.5.9.3 Interrupts on Forward Channel GPIO
        4. 7.5.9.4 Interrupts on Change in Sensor Status
        5. 7.5.9.5 Code Example to Readback Interrupts
        6. 7.5.9.6 CSI-2 Transmit Port Interrupts
      10. 7.5.10 Error Handling
        1. 7.5.10.1 Receive Frame Threshold
        2. 7.5.10.2 Port PASS Control
      11. 7.5.11 Timestamp – Video Skew Detection
      12. 7.5.12 Pattern Generation
        1. 7.5.12.1 Reference Color Bar Pattern
        2. 7.5.12.2 Fixed Color Patterns
        3. 7.5.12.3 Pattern Generator Programming
          1. 7.5.12.3.1 Determining Color Bar Size
        4. 7.5.12.4 Code Example for Pattern Generator
      13. 7.5.13 FPD-Link BIST Mode
        1. 7.5.13.1 BIST Operation
    6. 7.6 Register Maps
      1. 7.6.1 Main Registers
      2. 7.6.2 Indirect Access Registers
        1. 7.6.2.1 PATGEN_And_CSI-2 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 VDD Power Supply
      2. 8.4.2 Power-Up Sequencing
        1. 8.4.2.1 PDB Pin
        2. 8.4.2.2 System Initialization
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground
        2. 8.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 8.5.1.3 CSI-2 Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
POWER CONSUMPTION
PTTotal power consumption in operation modeCSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 1.664 Gbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 4.16 Gbps
CSI-2 mode, Non-replicate mode
Default registers		VDD18, VDD11, VDDIO800999mW
SUPPLY CURRENT
IDDT1Deserializer supply current (includes load current)CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 1.664 Gbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 4.16 Gbps
CSI-2 mode, Non-replicate mode
Default registers		VDD11165310mA
VDD18295340
VDDIO23
CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 832 Mbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 4.16 Gbps
CSI-2 mode, Non-replicate mode
Default registers		VDD11150290mA
VDD18295340
VDDIO23
IDDT2Deserializer supply current (includes load current)CSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 1.664 Gbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 4.16 Gbps
CSI-2 mode, Replicate mode
Default registers		VDD11174360mA
VDD18312370
VDDIO23
CSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 832 Mbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 4.16 Gbps
CSI-2 mode, Replicate mode
Default registers		VDD11127305mA
VDD18369415
VDDIO23
IDDT3Deserializer supply current (includes load current)CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 1.664 Gbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 1.867 Gbps
RAW12 HF mode, Non-replicate mode
Default registers		VDD11122300mA
VDD18263305
VDDIO23
CSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 832 Mbps
4 × FPD-Link III RX inputs
FPD-Link III line rate = 1.867 Gbps
RAW12 HF mode, Replicate mode
Default registers		VDD11120330mA
VDD18315365
VDDIO23
IDDZDeserializer shutdown currentPDB = LOWVDD11160mA
VDD184
VDDIO3
1.8-V LVCMOS I/O
VOHHigh level output voltageIOH = –2 mA, V(VDDIO) = 1.71 to 1.89 VGPIO[7:0]V(VDDIO) – 0.45V(VDDIO)V
VOLLow level output voltageIOL = 2 mA,  V(VDDIO) = 1.71 to 1.89 VGPIO[7:0], INTBGND0.45V
VIHHigh level input voltageV(VDDIO) = 1.71 to 1.89 VGPIO[7:0], PDB, REFCLK0.65 ×
V(VDDIO)		V(VDDIO)V
VILLow level input voltageGND0.35 ×
V(VDDIO)
IIHInput high currentVIN  =  V(VDDIO) = 1.71 to 1.89 V, internal pulldown enabledGPIO[7:0], PDB45115μA
VIN =  V(VDDIO) = 1.71 to 1.89 V, internal pulldown disabledGPIO[7:0], REFCLK20μA
IILInput low currentVIN  = 0 VGPIO[7:0], PDB, REFCLK–203.5μA
IIN-STRAPStrap pin input currentVIN  = 0 V to  V(VDD18)MODE, IDX–11μA
IOSOutput short circuit currentVOUT  = 0 VGPIO[7:0]–40mA
IOZTRI-STATE output currentVOUT = 0 V or V(VDDIO) , PDB = LOWGPIO[7:0]–2020μA
3.3-V LVCMOS I/O
VOHHigh level output voltageIOH = –4 mA, V(VDDIO) = 3.0 to 3.6 VGPIO[7:0]2.4V(VDDIO)V
VOLLow level output voltageIOL = 4 mA, V(VDDIO) = 3.0 to 3.6 VGPIO[7:0], INTBGND0.4V
VIHHighlevel input voltageV(VDDIO) = 3.0 to 3.6 VGPIO[7:0], REFCLK2V(VDDIO)V
 PDB1.17V(VDDIO)V
VILLow level input voltageV(VDDIO) = 3.0 to 3.6 VGPIO[7:0], REFCLKGND0.8V
PDBGND0.63V
IIHInput high currentVIN  =  V(VDDIO) = 3.0 to 3.6 V, internal pulldown enabledGPIO[7:0], PDB85215μA
VIN  =  V(VDDIO) = 3.0 to 3.6 V, internal pulldown disabledGPIO[7:0], REFCLK30μA
IILInput low currentVIN  =  V(VDDIO) = 0 VGPIO[7:0], PDB, REFCLK–203.5μA
IOSOutput short circuit currentVOUT  = 0 VGPIO[7:0]–65mA
IOZTRI-STATE output currentVOUT = 0 V or V(VDDIO) , PDB = LOWGPIO[7:0]–2030μA
I2C SERIAL CONTROL BUS
VIHInput high levelI2C_SDA, I2C_SCL
I2C_SDA2, I2C_SCL2		0.7 × V(I2C)V(I2C)V
VILInput low levelGND0.3 × V(I2C)V
VHYSInput hysteresis50mV
VOL1Output low levelV(I2C) = 3.0 to 3.6 V, IOL = 3 mAStandard-mode
Fast-mode		00.4V
V(I2C) = 3.0 to 3.6 V, IOL = 20 mAFast-mode Plus
VOL2Output low levelV(I2C) = 1.71 to 1.89 V, IOL = 2 mAFast-mode
Fast-mode Plus		00.2 × V(I2C)V
IINInput currentVIN = 0 V or V(I2C)–1010µA
CINInput capacitance5pF
FPD-LINK III RECEIVER INPUT
VCMCommon mode voltageRIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-1.2V
RTInternal termination resistanceSingle-ended RIN+ or RIN-405060Ω
Differential across RIN+ and RIN-80100120Ω
FPD-LINK III BACK CHANNEL DRIVER OUTPUT
VOUT-BCBack channel single-ended output voltageRL = 50 Ω
Coaxial configuration
Forward channel disabled		RIN0+, RIN1+
RIN2+, RIN3+		190220260mV
VOD-BCBack channel differential output voltage V(RIN+) - V(RIN-)RL = 100 Ω
STP configuration
Forward channel disabled		RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3-380440520mV
HSTX DRIVER
VCMTXHS transmit static common-mode voltageCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N,
CSI0_CLKP, CSI0_CLKN,
CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N,
CSI1_CLKP, CSI1_CLKN		150200250mV
|ΔVCMTX(1,0)|VCMTX mismatch when output is 1 or 05mVP-P
|VOD|HS transmit differential voltage140200270mV
|ΔVOD|VOD mismatch when output is 1 or 014mV
VOHHSHS output high voltage360mV
ZOSSingle-ended output impedance405062.5Ω
ΔZOSMismatch in single-ended output impedance10%
LPTX DRIVER
VOHHigh level output voltageCSI-2 TX line rate  ≤ 1.5 GbpsCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N,
CSI0_CLKP, CSI0_CLKN,
CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N,
CSI1_CLKP, CSI1_CLKN		1.11.21.3V
CSI-2 TX line rate > 1.5 Gbps0.951.3V
VOLLow level output voltage–5050mV
ZOLPOutput impedance110Ω
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