ZHCSIG1D August   2016  – September 2023 DS90UB960-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  CSI-2 Timing Specifications
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Receiver Port Control
        1. 7.4.5.1 Video Stream Forwarding
      6. 7.4.6  Input Jitter Tolerance
      7. 7.4.7  Adaptive Equalizer
        1. 7.4.7.1 Transmission Distance
        2. 7.4.7.2 Channel Requirements
        3. 7.4.7.3 Adaptive Equalizer Algorithm
        4. 7.4.7.4 AEQ Settings
          1. 7.4.7.4.1 AEQ Start-Up and Initialization
          2. 7.4.7.4.2 AEQ Range
          3. 7.4.7.4.3 AEQ Timing
          4. 7.4.7.4.4 AEQ Threshold
      8. 7.4.8  Channel Monitor Loop-Through Output Driver
        1. 7.4.8.1 Code Example for CMLOUT FPD3 RX Port 0:
      9. 7.4.9  RX Port Status
        1. 7.4.9.1 RX Parity Status
        2. 7.4.9.2 FPD-Link Decoder Status
        3. 7.4.9.3 RX Port Input Signal Detection
        4. 7.4.9.4 Line Counter
        5. 7.4.9.5 Line Length
      10. 7.4.10 Sensor Status
      11. 7.4.11 GPIO Support
        1. 7.4.11.1 GPIO Input Control and Status
        2. 7.4.11.2 GPIO Output Pin Control
        3. 7.4.11.3 Forward Channel GPIO
        4. 7.4.11.4 Back Channel GPIO
        5. 7.4.11.5 GPIO Pin Status
        6. 7.4.11.6 Other GPIO Pin Controls
      12. 7.4.12 RAW Mode LV / FV Controls
      13. 7.4.13 CSI-2 Protocol Layer
      14. 7.4.14 CSI-2 Short Packet
      15. 7.4.15 CSI-2 Long Packet
      16. 7.4.16 CSI-2 Data Identifier
      17. 7.4.17 Virtual Channel and Context
      18. 7.4.18 CSI-2 Mode Virtual Channel Mapping
        1. 7.4.18.1 Example 1
        2. 7.4.18.2 Example 2:
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Output Bandwidth
        1. 7.4.20.1 CSI-2 Output Bandwidth Calculation Example
      21. 7.4.21 CSI-2 Transmitter Status
      22. 7.4.22 Video Buffers
      23. 7.4.23 CSI-2 Line Count and Line Length
      24. 7.4.24 FrameSync Operation
        1. 7.4.24.1 External FrameSync Control
        2. 7.4.24.2 Internally Generated FrameSync
          1. 7.4.24.2.1 Code Example for Internally Generated FrameSync
      25. 7.4.25 CSI-2 Forwarding
        1. 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.25.2 Synchronized CSI-2 Forwarding
        3. 7.4.25.3 Basic Synchronized CSI-2 Forwarding
          1. 7.4.25.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 7.4.25.4 Line-Interleaved CSI-2 Forwarding
          1. 7.4.25.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 7.4.25.5 Line-Concatenated CSI-2 Forwarding
          1. 7.4.25.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 7.4.25.6 CSI-2 Replicate Mode
        7. 7.4.25.7 CSI-2 Transmitter Output Control
        8. 7.4.25.8 Enabling and Disabling CSI-2 Transmitters
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus
      2. 7.5.2  Second I2C Port
      3. 7.5.3  I2C Target Operation
      4. 7.5.4  Remote Target Operation
      5. 7.5.5  Remote Target Addressing
      6. 7.5.6  Broadcast Write to Remote Devices
        1. 7.5.6.1 Code Example for Broadcast Write
      7. 7.5.7  I2C Controller Proxy
      8. 7.5.8  I2C Controller Proxy Timing
        1. 7.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 7.5.9  Interrupt Support
        1. 7.5.9.1 Code Example to Enable Interrupts
        2. 7.5.9.2 FPD-Link III Receive Port Interrupts
        3. 7.5.9.3 Interrupts on Forward Channel GPIO
        4. 7.5.9.4 Interrupts on Change in Sensor Status
        5. 7.5.9.5 Code Example to Readback Interrupts
        6. 7.5.9.6 CSI-2 Transmit Port Interrupts
      10. 7.5.10 Error Handling
        1. 7.5.10.1 Receive Frame Threshold
        2. 7.5.10.2 Port PASS Control
      11. 7.5.11 Timestamp – Video Skew Detection
      12. 7.5.12 Pattern Generation
        1. 7.5.12.1 Reference Color Bar Pattern
        2. 7.5.12.2 Fixed Color Patterns
        3. 7.5.12.3 Pattern Generator Programming
          1. 7.5.12.3.1 Determining Color Bar Size
        4. 7.5.12.4 Code Example for Pattern Generator
      13. 7.5.13 FPD-Link BIST Mode
        1. 7.5.13.1 BIST Operation
    6. 7.6 Register Maps
      1. 7.6.1 Main Registers
      2. 7.6.2 Indirect Access Registers
        1. 7.6.2.1 PATGEN_And_CSI-2 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 VDD Power Supply
      2. 8.4.2 Power-Up Sequencing
        1. 8.4.2.1 PDB Pin
        2. 8.4.2.2 System Initialization
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground
        2. 8.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 8.5.1.3 CSI-2 Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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Pin Functions

Table 5-1 Pin Functions
PINI/O
TYPE		DESCRIPTION
NAMENO.
MIPI CSI-2 TX INTERFACE
CSI0_CLKN22OCSI-2 TX Port 0 differential clock output pins.
Leave unused pins as No Connect.
CSI0_CLKP23
CSI0_D0N24CSI-2 TX Port 0 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control.
Leave unused pins as No Connect.
CSI0_D0P25
CSI0_D1N26
CSI0_D1P27
CSI0_D2N28
CSI0_D2P29
CSI0_D3N30
CSI0_D3P31
CSI1_CLKN34OCSI-2 TX Port 1 differential clock output pins.
Leave unused pins as No Connect.
CSI1_CLKP35
CSI1_D0N36CSI-2 TX Port 1 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control.
Leave unused pins as No Connect.
CSI1_D0P37
CSI1_D1N38
CSI1_D1P39
CSI1_D2N40
CSI1_D2P41
CSI1_D3N42
CSI1_D3P43
FPD-LINK III RX INTERFACE
RIN0+50I/OFPD-Link III RX Port 0 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4.
If port is unused, set RX_PORT_CTL register bit 0 to 0 to disable RX Port 0 and leave the pins as No Connect.
RIN0-51
RIN1+53FPD-Link III RX Port 1 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4.
If port is unused, set RX_PORT_CTL register bit 1 to 0 to disable RX Port 1 and leave the pins as No Connect.
RIN1-54
RIN2+59FPD-Link III RX Port 2 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4.
If port is unused, set RX_PORT_CTL register bit 2 to 0 to disable RX Port 2 and leave the pins as No Connect.
RIN2-60
RIN3+62FPD-Link III RX Port 3 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible FPD-Link III serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4.
If port is unused, set RX_PORT_CTL register bit 3 to 0 to disable RX Port 3 and leave the pins as No Connect.
RIN3-63
SYNCHRONIZATION AND GENERAL-PURPOSE I/O
GPIO09I/O, PDGeneral-Purpose Input/Output pins. The pins can be used to control and respond to various commands. They may be configured to be input signals for the corresponding GPIOs on the serializer or they may be configured to be outputs to follow local register settings. At power up, the GPIO pins are disabled and by default include a pulldown resistor (25-kΩ typ).
See Section 7.4.11. for programmability. If unused, leave the pin as No Connect.
GPIO110
GPIO214
GPIO315
GPIO417
GPIO518
GPIO619
GPIO720
INTB6O, ODInterrupt Output pin.
INTB is an active-low open drain and controlled by the status registers. See Section 7.5.9.
Recommend a 4.7-kΩ Pullup to 1.8 V or 3.3 V. If unused, leave the pin as No Connect.
SERIAL CONTROL BUS (I2C)
I2C_SCL 12 I/O, OD Primary I2C Clock Input / Output interface pin. See Section 7.5.1.
Refer to "I2C Bus Pullup Resistor Calculation" (SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
I2C_SDA 11 I/O, OD Primary I2C Data Input / Output interface pin. See Section 7.5.1.
Refer to "I2C Bus Pullup Resistor Calculation" (SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
I2C_SCL2 8 I/O, OD Secondary I2C Clock Input / Output interface pin. See Section 7.5.2.
Refer to "I2C Bus Pullup Resistor Calculation" (SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
I2C_SDA2 7 I/O, OD Secondary I2C Data Input / Output interface pin. See Section 7.5.2.
Refer to "I2C Bus Pullup Resistor Calculation" (SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
CONFIGURATION AND CONTROL
IDX46SI2C Serial Control Bus Device ID Address Select configuration pin.
Connect to an external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 7-18.
MODE45SMode Select configuration pin.
Connect to external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 7-2.
PDB3I, PDInverted Power-Down input pin. Typically connected to a processor GPIO with a pulldown. When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an internal 50-kΩ internal pulldown enabled. PDB should remain low until after power supplies are applied and reach minimum required levels. See Section 8.4.1.
INPUT IS 3.3-V TOLERANT
PDB = 1.8 V, device is enabled (normal operation)
PDB = 0 V, device is powered down.
POWER AND GROUND
VDDIO16P1.8-V (±5%) OR 3.3-V (±10%) LVCMOS I/O Power
Requires 1-μF and 0.1-μF or 0.01-μF capacitors to GND.
VDD_CSI0
VDD_CSI1		21
33		P1.1-V (±5%) Power Supplies
Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF and 10-μF decoupling is recommended for the pin group.
VDDL1
VDDL2		13
44		P1.1-V (±5%) Power Supplies
Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF and 10-μF decoupling is recommended for the pin group.
VDD_FPD1
VDD_FPD2		52
61		P1.1-V (±5%) Power Supplies
Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF and 10-μF decoupling is recommended for the pin group.
VDD18_P2
VDD18_P3
VDD18_P1
VDD18_P0		2
1
47
48		P1.8-V (±5%) Power Supplies
Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF, and 10-μF decoupling is recommended for the pin group.
VDD18A32P1.8-V (±5%) Power Supplies
Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF, and 10-μF decoupling is recommended for the pin group.
VDD18_FPD0
VDD18_FPD1
VDD18_FPD2
VDD18_FPD3		49
55
58
64		P1.8-V (±5%) Power Supplies
Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF, and 10-μF decoupling is recommended for the pin group.
GNDDAPGDAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND).
OTHERS
REFCLK5IReference clock oscillator input.
Typically connected to a 23-MHz to 26-MHz LVCMOS-level oscillator (100 ppm).
For 400-Mbps, 800-Mbps, 1.2-Gbps or 1.6-Gbps CSI-2 data rates, use 25-MHz frequency.
For the oscillator requirements, see Section 7.4.4. For other common CSI-2 data rates, see Section 7.4.19.
RES4-This pin must be tied to GND for normal operation.
CMLOUTP56OChannel Monitor Loop-through Driver differential output.
Route to a test point or a pad with 100-Ω termination resistor between pins for channel monitoring (recommended). See Section 7.4.8.
CMLOUTN57
The definitions below define the functionality of the I/O cells for each pin. TYPE:
  • I = Input
  • O = Output
  • I/O = Input/Output
  • S = Strap Input
  • PD = Internal Pulldown
  • OD = Open Drain
  • P = Power Supply
  • G = Ground
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