米6体育平台手机版

ZHCSAP4M October 2010 – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

NKB|60
- MPQS030A

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
Supply voltage – V_DD33		−0.3	4	V
Supply voltage – V_DDIO		−0.3	4	V
LVCMOS I/O voltage		−0.3	(V_DDIO + 0.3)	V
Deserializer input voltage		−0.3	2.75	V
Junction temperature			150	°C
60-pin WQFN Package Maximum power dissipation capacity at 25°C	Derate above 25 °C		1/ R_θJA	°C/W
	R_θJA		31	°C/W
	R_θJC		2.4	°C/W
Storage temperature, T_stg		−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

(3) For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±8000	V
		Charged-device model (CDM), per AEC Q100-011		±1250
		Machine model, all pins		±250
		(IEC, powered-up only) R_D = 330 Ω, C_S = 150 pF	Air Discharge (Pin 49 and 50)	±15000
		(IEC, powered-up only) R_D = 330 Ω, C_S = 150 pF	Contact Discharge (Pin 49 and 50)	±8000
		(ISO10605) R_D = 330 Ω, C_S = 150 pF	Air Discharge (Pin 49 and 50)	±15000
		(ISO10605) R_D = 330 Ω, C_S = 150 pF	Contact Discharge (Pin 49 and 50)	±8000
		(ISO10605) R_D = 2 kΩ, C_S = 150 & 330 pF	Air Discharge (Pin 49 and 50)	±15000
		(ISO10605) R_D = 2 kΩ, C_S = 150 & 330 pF	Contact Discharge (Pin 49 and 50)	±8000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
Supply voltage (V_DD33)		3	3.3	3.6	V
LVCMOS supply voltage (V_DDIO)	Connect V_DDIO to 3.3 V and use 3.3-V IOs	3	3.3	3.6	V
LVCMOS supply voltage (V_DDIO)	Connect V_DDIO to 1.8 V and use 1.8-V IOs	1.71	1.8	1.89	V
Operating free air temperature (T_A)		−40	25	105	°C
PCLK frequency		5		85	MHz
Supply noise⁽¹⁾				100	mV_P-P

(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the V_DD33 and V_DDIO supplies with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90UH926Q-Q1	UNIT
		NKB (WQFN)
		60 PINS
R_θJA	Junction-to-ambient thermal resistance	26.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	8.1	°C/W
R_θJB	Junction-to-board thermal resistance	5.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	5.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.1	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS		PIN/FREQ.	MIN	TYP	MAX	UNIT
LVCMOS I/O DC SPECIFICATIONS
V_IH	High Level Input Voltage	V_DDIO = 3 to 3.6 V		PDB	2		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3 to 3.6 V			GND		0.8	V
I_IN	Input Current	V_IN = 0 V or V_DDIO = 3 to 3.6 V			−10	±1	10	μA
V_IH	High Level Input Voltage	V_DDIO = 3 to 3.6 V		OEN, OSS_SEL, BISTEN, BISTC / INTB_IN, GPIO[3:0]	2		V_DDIO	V
V_IH	High Level Input Voltage	V_DDIO = 1.71 to 1.89 V			0.65 × V_DDIO		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3 to 3.6 V			GND		0.8	V
V_IL	Low Level Input Voltage	V_DDIO = 1.71 to 1.89 V			GND		0.35 × V_DDIO	V
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 3 to 3.6 V		−10	±1	10	μA
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 1.7 to 1.89 V		−10	±1	10	μA
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 3 to 3.6 V	R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB, GPO_REG[8:4]	2.4		V_DDIO	V
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 1.7 to 1.89 V		V_DDIO- 0.45		V_DDIO	V
V_OL	Low Level Output Voltage	I_OL = 4 mA	V_DDIO = 3 to 3.6 V		GND		0.4	V
V_OL	Low Level Output Voltage	I_OL = 4 mA	V_DDIO = 1.7 to 1.89 V		GND		0.35	V
I_OS	Output Short-Circuit Current	V_OUT = 0 V				−60		mA
I_OZ	Tri-state Output Current	V_OUT = 0 V or V_DDIO, PDB = L			−10		10	μA
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
V_TH	Differential Threshold High Voltage	V_CM = 2.5 V (Internal V_BIAS)		RIN+, RIN–			50	mV
V_TL	Differential Threshold Low Voltage	V_CM = 2.5 V (Internal V_BIAS)			−50			mV
V_CM	Differential Common-mode Voltage					1.8		V
R_T	Internal Termination Resistor - Differential				80	100	120	Ω
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
V_ODp-p	Differential Output Voltage	R_L = 100 Ω		CMLOUTP, CMLOUTN	360			mVp-p
SUPPLY CURRENT
I_DD1	Supply Current (includes load current) f = 85 MHz	C_L = 12 pF, Checker Board Pattern Figure 1	V_DD33= 3.6 V	V_DD33		125	145	mA
I_DDIO1			V_DDIO= 3.6 V	V_DDIO		110	118	mA
I_DDIO1			V_DDIO = 1.89 V	V_DDIO		60	75	mA
I_DD2	Supply Current (includes load current) f = 85 MHz	C_L = 4 pF Checker Board Pattern, Figure 1	V_DD33 = 3.6 V	V_DD33		125	145	mA
I_DDIO2			V_DDIO = 3.6 V	V_DDIO		75	85	mA
I_DDIO2			V_DDIO = 1.89 V	V_DDIO		50	65	mA
I_DDS	Supply Current Sleep Mode	Without Input Serial Stream	V_DD33 = 3.6 V	V_DD33		90	115	mA
I_DDIOS			V_DDIO = 3.6 V	V_DDIO		3	5	mA
I_DDIOS			V_DDIO = 1.89 V	V_DDIO		2	3	mA
I_DDZ	Supply Current Power Down	PDB = L, All LVCMOS inputs are floating or tied to GND	V_DD33 = 3.6 V	V_DD33		2	10	mA
I_DDIOZ			V_DDIO = 3.6 V	V_DDIO		0.05	10	mA
I_DDIOZ			V_DDIO = 1.89 V	V_DDIO		0.05	10	mA

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(2) Typical values represent most likely parametric norms at V_DD = 3.3 V, T_A = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
GPIO BIT RATE
B_R	Forward Channel Bit Rate	See⁽⁴⁾ ⁽⁵⁾	f = 5 – 85 MHz, GPIO[3:0]		0.25 × f		Mbps
B_R	Back Channel Bit Rate	See⁽⁴⁾ ⁽⁵⁾	f = 5 – 85 MHz, GPIO[3:0]	> 50	> 75		kbps
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
E_W	Differential Output Eye Opening Width⁽⁶⁾	R_L = 100 Ω, Jitter Freq > f / 40 Figure 2 ⁽⁴⁾⁽⁵⁾	CMLOUTP, CMLOUTN, f = 85 MHz	0.3	0.4		UI
E_H	Differential Output Eye Height	R_L = 100 Ω, Jitter Freq > f / 40 Figure 2 ⁽⁴⁾⁽⁵⁾	CMLOUTP, CMLOUTN, f = 85 MHz	200	300		mV
BIST MODE
t_PASS	BIST PASS Valid Time BISTEN = H Figure 8 ⁽⁴⁾⁽⁵⁾		PASS		800		ns
SSCG MODE
f_DEV	Spread Spectrum Clocking Deviation Frequency	SeeFigure 14, Table 1 and Table 2 ⁽⁴⁾⁽⁵⁾	f = 85 MHz, SSCG = ON	±0.5%		±2.5%
f_MOD	Spread Spectrum Clocking Modulation Frequency	SeeFigure 14, Table 1 and Table 2 ⁽⁴⁾⁽⁵⁾	f = 85 MHz, SSCG = ON	8		100	kHz

(2) Typical values represent most likely parametric norms at V_DD = 3.3 V, T_A = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

(4) Specification is ensured by characterization and is not tested in production.

(5) Specification is ensured by design and is not tested in production.

(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency.

6.7 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified.⁽¹⁾ ⁽²⁾ ⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Level	SDA and SCL	0.7 × V_DD33		V_DD33	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.3 × V_DD33	V
V_HY	Input Hysteresis			> 50		mV
V_OL		SDA, IOL = 1.25 mA	0		0.36	V
I_IN		SDA or SCL, V_IN = V_DD33 or GND	–10		10	µA
t_R	SDA Rise Time – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9		430		ns
t_F	SDA Fall Time – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9		20		ns
t_SU;DAT	Setup Time — READ	SeeFigure 9		560		ns
t_HD;DAT	Holdup Time — READ	SeeFigure 9		615		ns
t_SP	Input Filter			50		ns
C_IN	Input Capacitance	SDA or SCL		<5		pF

(2) Typical values represent most likely parametric norms at V_DD = 3.3 V, T_A = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

6.8 Recommended Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.

			MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	Standard Mode	0	100	kHz
f_SCL	SCL Clock Frequency	Fast Mode	0	400	kHz
t_LOW	SCL Low Period	Standard Mode	4.7		µs
t_LOW	SCL Low Period	Fast Mode	1.3		µs
t_HIGH	SCL High Period	Standard Mode	4		µs
t_HIGH	SCL High Period	Fast Mode	0.6		µs
t_HD;STA	Hold time for a start or a repeated start condition Figure 9	Standard Mode	4		µs
t_HD;STA		Fast Mode	0.6		µs
t_SU:STA	Setup time for a start or a repeated start condition Figure 9	Standard Mode	4.7		µs
t_SU:STA		Fast Mode	0.6		µs
t_HD;DAT	Data Hold Time Figure 9	Standard Mode	0	3.45	µs
t_HD;DAT	Data Hold Time Figure 9	Fast Mode	0	0.9	µs
t_SU;DAT	Data Setup Time Figure 9	Standard Mode	250		ns
t_SU;DAT	Data Setup Time Figure 9	Fast Mode	100		ns
t_SU;STO	Setup Time for STOP Condition, Figure 9	Standard Mode	4		µs
t_SU;STO	Setup Time for STOP Condition, Figure 9	Fast Mode	0.6		µs
t_BUF	Bus Free Time Between STOP and START, Figure 9	Standard Mode	4.7		µs
t_BUF	Bus Free Time Between STOP and START, Figure 9	Fast Mode	1.3		µs
t_r	SCL and SDA Rise Time, Figure 9	Standard Mode		1000	ns
t_r	SCL and SDA Rise Time, Figure 9	Fast Mode		300	ns
t_f	SCL and SDA Fall Time, Figure 9	Standard Mode		300	ns
t_f	SCL and SDA Fall Time, Figure 9	Fast mode		300	ns

6.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
t_RCP	PCLK Output Period	t_RCP = t_TCP	PCLK	11.76	T	200	ns
t_RDC	PCLK Output Duty Cycle		PCLK	45%	50%	55%
t_CLH	LVCMOS Low-to-High Transition Time Figure 3	V_DDIO = 1.71 to 1.89 V, C_L = 12 pF	R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB		2	3	ns
t_CLH	LVCMOS Low-to-High Transition Time Figure 3	V_DDIO = 3 to 3.6 V, C_L = 12 pF			2	3	ns
t_CHL	LVCMOS High-to-Low Transition Time Figure 3	V_DDIO = 1.71 to 1.89 V, C_L = 12 pF			2	3	ns
t_CHL	LVCMOS High-to-Low Transition Time Figure 3	V_DDIO = 3 to 3.6 V, C_L = 12 pF			2	3	ns
t_ROS	Data Valid before PCLK – Setup Time SSCG = OFF Figure 6	V_DDIO = 1.71 to 1.89 V, C_L = 12 pF		2.2			ns
t_ROS	Data Valid before PCLK – Setup Time SSCG = OFF Figure 6	V_DDIO = 3 to 3.6 V, C_L = 12 pF		2.2			ns
t_ROH	Data Valid after PCLK – Hold Time SSCG = OFF Figure 6	V_DDIO = 1.71 to 1.89 V, C_L = 12 pF		3			ns
t_ROH	Data Valid after PCLK – Hold Time SSCG = OFF Figure 6	V_DDIO = 3 to 3.6 V, C_L = 12 pF		3			ns
t_XZR	Active to OFF Delay Figure 5⁽²⁾⁽³⁾	OEN = L, OSS_SEL = H	R[7:0], G[7:0], B[7:0]		10		ns
			HS, VS, DE, PCLK, LOCK, PASS		15		ns
			MCLK,I2S_CLK, I2S_WC, I2S_DA, I2S_DB		60		ns
t_DDLT	Lock Time Figure 5⁽²⁾⁽³⁾⁽¹⁾	SSCG = OFF	f = 5 – 85 MHz		5	40	ms
t_DD	Delay – Latency⁽²⁾⁽³⁾		f = 5 – 85 MHz		147 × T		ns
t_DCCJ	Cycle-to-Cycle Jitter⁽²⁾⁽³⁾	SSCG = OFF	f = 5 to <15 MHz		0.5		ns
			f = 15 to 85 MHz		0.2		ns
			I2S_CLK = 1 to 12.28 MHz		±2		ns
t_ONS	Data Valid After OEN = H SetupTime Figure 7⁽²⁾⁽³⁾	VDDIO = 1.71 to 1.89 V, CL = 12 pF	R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, MCLK,I2S_CLK, I2S_WC, I2S_DA, I2S_DB		50		ns
t_ONS	Data Valid After OEN = H SetupTime Figure 7⁽²⁾⁽³⁾	VDDIO = 3 to 3.6 V, CL = 12 pF			50		ns
t_ONH	Data Tri-State After OEN = L SetupTime Figure 7 ⁽²⁾ ⁽³⁾	VDDIO = 1.71 to 1.89 V, CL = 12 pF			50		ns
t_ONH	Data Tri-State After OEN = L SetupTime Figure 7 ⁽²⁾ ⁽³⁾	VDDIO = 3 to 3.6 V, CL = 12 pF			50		ns
t_SES	Data Tri-State after OSS_ SEL = H, Setup Time Figure 7 ⁽²⁾ ⁽³⁾	VDDIO = 1.71 to 1.89 V, CL = 12 pF			5		ns
t_SES		VDDIO = 3 to 3.6 V, CL = 12 pF			5		ns
t_SEH	Data to Low after OSS_SEL = L Setup Time Figure 7 ⁽²⁾ ⁽³⁾	VDDIO = 1.71 to 1.89 V, CL = 12 pF			5		ns
t_SEH	Data to Low after OSS_SEL = L Setup Time Figure 7 ⁽²⁾ ⁽³⁾	VDDIO = 3 to 3.6 V, CL = 12 pF			5		ns