ZHCSDB4B MARCH   2013  – January 2015 DS90UH928Q-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 应用图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  Timing Requirements for the Serial Control Bus
    8. 7.8  Timing Requirements
    9. 7.9  DC and AC Serial Control Bus Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Speed Forward Channel Data Transfer
      2. 8.3.2  Low Speed Back Channel Data Transfer
      3. 8.3.3  Backward Compatible Mode
      4. 8.3.4  Input Equalization
      5. 8.3.5  Common Mode Filter Pin (CMF)
      6. 8.3.6  Power Down (PDB)
      7. 8.3.7  Video Control Signals
      8. 8.3.8  EMI Reduction Features
        1. 8.3.8.1 LVCMOS VDDIO Option
      9. 8.3.9  Built In Self Test (BIST)
        1. 8.3.9.1 BIST Configuration and Status
          1. 8.3.9.1.1 Sample BIST Sequence
        2. 8.3.9.2 Forward Channel and Back Channel Error Checking
      10. 8.3.10 Internal Pattern Generation
        1. 8.3.10.1 Pattern Options
        2. 8.3.10.2 Color Modes
        3. 8.3.10.3 Video Timing Modes
        4. 8.3.10.4 External Timing
        5. 8.3.10.5 Pattern Inversion
        6. 8.3.10.6 Auto Scrolling
        7. 8.3.10.7 Additional Features
      11. 8.3.11 Image Enhancement Features
        1. 8.3.11.1 White Balance
          1. 8.3.11.1.1 LUT Contents
          2. 8.3.11.1.2 Enabling White Balance
        2. 8.3.11.2 Adaptive Hi-FRC Dithering
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Oscillator Output
      14. 8.3.14 Interrupt Pin (INTB)
      15. 8.3.15 General-Purpose I/O
        1. 8.3.15.1 GPIO[3:0]
        2. 8.3.15.2 GPIO[8:5]
      16. 8.3.16 I2S Audio Interface
        1. 8.3.16.1 I2S Transport Modes
        2. 8.3.16.2 I2S Repeater
        3. 8.3.16.3 I2S Jitter Cleaning
        4. 8.3.16.4 MCLK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock and Output Status
      2. 8.4.2 FPD-Link Input Frame and Color Bit Mapping Select
      3. 8.4.3 Low Frequency Optimization (LFMODE)
      4. 8.4.4 Mode Select (MODE_SEL)
      5. 8.4.5 Repeater Connections
        1. 8.4.5.1 Repeater Fan-Out Electrical Requirements
      6. 8.4.6 HDCP I2S Audio Encryption
      7. 8.4.7 Repeater Configuration
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transmission Media
        2. 9.2.2.2 Display Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 CML Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

RHS Package
48-Pin WQFN
Top View
DS90UH928Q-Q1 DS90UH928Q_PIN_DIAGRAM.gif

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NO.
FPD-LINK OUTPUT INTERFACE
TxCLKOUT- 18 O, LVDS Inverting LVDS Clock Output
The pair requires external 100Ω differential termination for standard LVDS levels
TxCLKOUT+ 17 O, LVDS True LVDS Clock Output
The pair requires external 100Ω differential termination for standard LVDS levels
TxOUT[3:0]- 16, 20, 22, 24 O, LVDS Inverting LVDS Data Outputs
Each pair requires external 100Ω differential termination for standard LVDS levels
TxOUT[3:0]+ 15, 19, 21, 23 O, LVDS True LVDS Data Outputs
Each pair requires external 100Ω differential termination for standard LVDS levels
LVCMOS INTERFACE
GPIO[1:0] 13, 14 I/O, LVCMOS
with pulldown		 General Purpose IO
GPIO[3:2] 36, 37 I/O, LVCMOS
with pulldown		 General Purpose I/O
Shared with I2S_DD, I2S_DC
GPIO_REG[8:5] 8, 10, 7, 3 I/O, LVCMOS
with pulldown		 General Purpose I/O, register access only
Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
I2S_DA
I2S_DB
I2S_DC
I2S_DD		 7
3
37
36		 O, LVCMOS Digital Audio Interface I2S Data Outputs
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
INTB_IN 43 I, LVCMOS
with pulldown		 HDCP Interrupt Input
Shared with BISTC
MCLK
I2S_WC
I2S_CLK		 11
10
8		 O, LVCMOS Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs
I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8
CONTROL AND CONFIGURATION
BISTC 43 I, LVCMOS
with pulldown		 BIST Clock Select
Shared with INTB_IN
Requires a 10-kΩ pullup if set HIGH
BISTEN 9 I, LVCMOS
with pulldown		 BIST Enable
Requires a 10-kΩ pullup if set HIGH
IDx 12 I, Analog I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Table 6
LFMODE 32 I, LVCMOS
with pulldown		 Low Frequency Mode Select
LFMODE = 0, 15 MHz ≤ TxCLKOUT ≤ 85 MHz (Default)
LFMODE = 1, 5 MHz ≤ TxCLKOUT < 15 MHz
Requires a 10-kΩ pullup if set HIGH
MAPSEL 26 I, LVCMOS
with pulldown		 FPD-Link Output Map Select
MAPSEL = 0, LSBs on TxOUT3± (Default)
MAPSEL = 1, MSBs on TxOUT3±
Requires a 10-kΩ pullup if set HIGH
MODE_SEL 48 I, Analog Device Configuration Select
Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4-channel (I2S_B), and Long Cable (LCBL) modes
Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage divider. DO NOT FLOAT
See Table 5
OEN 30 I, LVCMOS
with pulldown		 Output Enable
Requires a 10-kΩ pullup if set HIGH
See Table 4
OSS_SEL 35 I, LVCMOS
with pulldown		 Output Sleep State Select
Requires a 10-kΩ pullup if set HIGH
See Table 4
PDB 1 I, LVCMOS Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to “Power Up Requirements and PDB Pin" in the Applications Information Section.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down
When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state, the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
SCL 5 I/O, Open Drain I2C Clock Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
SDA 4 I/O, Open Drain I2C Data Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
STATUS
LOCK 27 O, LVCMOS LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (Recommended). Float if unused.
PASS 28 O, LVCMOS PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
FPD-LINK III SERIAL INTERFACE
CMF 42 Analog Common Mode Filter
Requires a 0.1-µF capacitor to GND
CMLOUTN 45 O, LVDS Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal
CMLOUTP 44 O, LVDS True Loop-through Driver Output
Monitor point for equalized forward channel differential signal
RIN- 41 I/O, LVDS FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1-µF capacitor
RIN+ 40 I/O, LVDS FPD-Link III True Input
The output must be AC-coupled with a 0.1-µF capacitor
POWER AND GROUND(1)
GND DAP Ground Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
VDD33_A
VDD33_B		 38
31		 Power 3.3-V Power to on-chip regulator
Each pin requires a 4.7-µF capacitor to GND
VDDIO 6 Power 1.8 V/3.3 V LVCMOS I/O Power
Requires a 4.7-µF capacitor to GND
REGULATOR CAPACITOR
CAPI2S
CAPLV25
CAPLV12
CAPR12
CAPP12		 2
25
29
46
47		 CAP Decoupling capacitor connection for on-chip regulator
Each requires a 4.7-µF decoupling capacitor to GND
CAPL12 33 CAP Decoupling capacitor connection for on-chip regulator
Requires two 4.7-µF decoupling capacitors to GND
OTHER
RES[1:0] 39, 34 GND Reserved
Connect to GND
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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