ZHCSD35B November   2014  – August 2019 DS90UH949-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用图表
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC And AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Definition Multimedia Interface (HDMI)
        1. 7.3.1.1 HDMI Receive Controller
      2. 7.3.2  Transition Minimized Differential Signaling
      3. 7.3.3  Enhanced Display Data Channel
      4. 7.3.4  Extended Display Identification Data (EDID)
        1. 7.3.4.1 External Local EDID (EEPROM)
        2. 7.3.4.2 Internal EDID (SRAM)
        3. 7.3.4.3 External Remote EDID
        4. 7.3.4.4 Internal Pre-Programmed EDID
      5. 7.3.5  Consumer Electronics Control (CEC)
      6. 7.3.6  +5-V Power Signal
      7. 7.3.7  Hot Plug Detect (HPD)
      8. 7.3.8  High-Speed Forward Channel Data Transfer
      9. 7.3.9  Back Channel Data Transfer
      10. 7.3.10 FPD-Link III Port Register Access
      11. 7.3.11 Power Down (PDB)
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Interrupt Pin (INTB)
      14. 7.3.14 Remote Interrupt Pin (REM_INTB)
      15. 7.3.15 General-Purpose I/O
        1. 7.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.15.2 Back Channel Configuration
        3. 7.3.15.3 GPIO_REG[8:5] Configuration
      16. 7.3.16 SPI Communication
        1. 7.3.16.1 SPI Mode Configuration
        2. 7.3.16.2 Forward Channel SPI Operation
        3. 7.3.16.3 Reverse Channel SPI Operation
      17. 7.3.17 Backward Compatibility
      18. 7.3.18 Audio Modes
        1. 7.3.18.1 HDMI Audio
        2. 7.3.18.2 DVI I2S Audio Interface
          1. 7.3.18.2.1 I2S Transport Modes
          2. 7.3.18.2.2 I2S Repeater
        3. 7.3.18.3 AUX Audio Channel
        4. 7.3.18.4 TDM Audio Interface
      19. 7.3.19 HDCP
        1. 7.3.19.1 HDCP I2S Audio Encryption
      20. 7.3.20 Built-In Self Test (BIST)
        1. 7.3.20.1 BIST Configuration And Status
        2. 7.3.20.2 Forward Channel and Back Channel Error Checking
      21. 7.3.21 Internal Pattern Generation
        1. 7.3.21.1 Pattern Options
        2. 7.3.21.2 Color Modes
        3. 7.3.21.3 Video Timing Modes
        4. 7.3.21.4 External Timing
        5. 7.3.21.5 Pattern Inversion
        6. 7.3.21.6 Auto Scrolling
        7. 7.3.21.7 Additional Features
      22. 7.3.22 Spread Spectrum Clock Tolerance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. 7.4.2.1 Single Link Operation
        2. 7.4.2.2 Dual Link Operation
        3. 7.4.2.3 Replicate Mode
        4. 7.4.2.4 Auto-Detection of FPD-Link III Modes
      3. 7.4.3 Frequency Detection Circuit May Reset the FPD-Link III PLL During a Temperature Ramp
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Register Maps

Table 10. Serial Control Bus Registers

ADD
(dec)		 ADD
(hex)		 REGISTER NAME BIT(S) REGISTER
TYPE		 DEFAULT
(hex)		 FUNCTION DESCRIPTION
0 0x00 I2C Device ID 7:1 RW Strap DEVICE_ID 7-bit address of Serializer. Defaults to address configured by the IDx strap pin.
0 RW 0x00 ID Setting I2C ID setting.
0: Device I2C address is from IDx strap pin (default).
1: Device I2C address is from 0x00[7:1].
1 0x01 Reset
A software I2C reset command issued by writing to register 0x01 is supported only when operating I2C in the 3.3V mode.		 7:5 0x00 Reserved.
4 RW HDMI Reset HDMI Digital Reset.
Resets the HDMI digital block. This bit is self-clearing.
0: Normal operation.
1: Reset.
3:2 Reserved.
1 RW Digital RESET1 Reset the entire digital block including registers. This bit is self-clearing.
0: Normal operation (default).
1: Reset.
Following the setting of this bit, the software should also set bit 0x4F[1] (BRIDGE_CTL register). This will restore register values that are initially loaded from Non-Volatile Memory to their default state.
0 RW Digital RESET0 Reset the entire digital block except registers. This bit is self-clearing.
0: Normal operation (default).
1: Reset.
Registers which are loaded by pin strap will be restored to their original strap value when this bit is set. These registers show 'Strap' as their default value in this table.
Registers 0x00, 0x13, 0x15, 0x18, 0x19, 0x1A, 0x48-0x55, 0x58, 0x5B, 0xC0, 0xC2, 0xC3, 0xC6, 0xC8, 0xCE and 0xD0 are also restored to their default value when this bit is set.
3 0x03 General Configuration 7 RW 0xD2 Back channel CRC Checker Enable Enable/disable back channel CRC Checker.
0: Disable.
1: Enable (default).
6 Reserved.
5 RW I2C Remote Write Auto Acknowledge
Port0/Port1 		Automatically acknowledge I2C remote writes. When enabled, I2C writes to the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the Deserializer to acknowledge the write. This allows higher throughput on the I2C bus. Note: this mode will prevent any NACK from a remote device from reaching the I2C master.
0: Disable (default).
1: Enable.
If PORT1_SEL is set, this register controls Port1 operation.
4 RW Filter Enable HS, VS, DE two-clock filter. When enabled, pulses less than two full TMDS clock cycles on the DE, HS, and VS inputs will be rejected.
0: Filtering disable.
1: Filtering enable (default).
3 RW I2C Pass-through
Port0/Port1 		I2C pass-through mode. Read/Write transactions matching any entry in the Slave Alias registers will be passed through to the remote Deserializer.
0: Pass-through disabled (default).
1: Pass-through enabled.
If PORT1_SEL is set, this register controls Port1 operation.
2 Reserved.
1 RW TMDS Clock Auto Switch over to internal oscillator in the absence of TMDS Clock.
0: Disable auto-switch.
1: Enable auto-switch (default).
0 Reserved.
4 0x04 Mode Select 7 RW 0x80 Failsafe State Input failsafe state.
0: Failsafe to High.
1: Failsafe to Low (default).
6 Reserved.
5 RW CRC Error Reset Clear back channel CRC Error counters. This bit is NOT self-clearing.
0: Normal operation (default).
1: Clear counters.
4 Video gate Reserved.
3:0 Reserved.
5 0x05 I2C Control 7:5 0x00 Reserved.
4:3 RW SDA Output Delay Configures output delay on the SDA output. Setting this value will increase output delay in units of 40ns.
Nominal output delay values for SCL to SDA are:
00: 240ns (default).
01: 280ns.
10: 320ns.
11: 360ns.
2 RW Local Write Disable Disable remote writes to local registers. Setting this bit to 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Serializer registers from an I2C master attached to the Deserializer. Setting this bit does not affect remote access to I2C slaves at the Serializer.
0: Enable (default).
1: Disable.
1 RW I2C Bus Timer Speedup Speed up I2C bus Watchdog Timer.
0: Watchdog Timer expires after approximately 1s (default).
1: Watchdog Timer expires after approximately 50µs.
0 RW I2C Bus Timer Disable Disable I2C bus Watchdog Timer. The I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1s, the I2C bus will be assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL.
0: Enable (default).
1: Disable.
6 0x06 DES ID 7:1 RW 0x00 DES Device ID
Port0/Port1 		7-bit I2C address of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates the Deserializer Device ID for the Deserializer attached to Port1.
0 RW Freeze Device ID
Port0/Port1 		Freeze Deserializer Device ID.
1: Prevents auto-loading of the Deserializer Device ID by the Bidirectional Control Channel. The ID will be frozen at the value written.
0: Allows auto-loading of the Deserializer Device ID from the Bidirectional Control Channel.
If PORT1_SEL is set, this register is with reference to Port1.
7 0x07 Slave ID[0] 7:1 RW 0x00 Slave ID 0
Port0/Port1 		7-bit I2C address of the remote Slave 0 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 0.
If PORT1_SEL is set, this register is with reference to Port1.
0 Reserved.
8 0x08 Slave Alias[0] 7:1 RW 0x00 Slave Alias ID 0
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 0 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 0 register. A value of 0 in this field disables access to the remote Slave 0.
If PORT1_SEL is set, this register is with reference to Port1.
0 Reserved.
10 0x0A CRC Errors 7:0 R 0x00 CRC Error LSB
Port0/Port1 		Number of back channel CRC errors – 8 least significant bits. Cleared by 0x04[5].
If PORT1_SEL is set, this register is with reference to Port1.
11 0x0B 7:0 R 0x00 CRC Error MSB
Port0/Port1 		Number of back channel CRC errors – 8 most significant bits. Cleared by 0x04[5].
If PORT1_SEL is set, this register is with reference to Port1.
12 0x0C General Status 7:5 Reserved.
4 0x00 Link Lost
Port0/Port1 		Link lost flag for selected port:
This bit indicates that loss of link has been detected. This register bit will stay high until cleared using the CRC Error Reset in register 0x04.
If PORT1_SEL is set, this register is with reference to Port1.
3 R BIST CRC Error
Port0/Port1 		Back channel CRC error(s) during BIST communication with Deserializer. This bit is cleared upon loss of link, restart of BIST, or assertion of CRC Error Reset bit in 0x04[5].
0: No CRC errors detected during BIST.
1: CRC error(s) detected during BIST.
If PORT1_SEL is set, this register is with reference to Port1.
2 R TMDS Clock Detect Pixel clock status:
0: Valid clock not detected at HDMI input.
1: Valid clock detected at HDMI input.
1 R DES Error
Port0/Port1 		CRC error(s) during normal communication with Deserializer. This bit is cleared upon loss of link or assertion of 0x04[5].
0: No CRC errors detected.
1: CRC error(s) detected.
If PORT1_SEL is set, this register is with reference to Port1.
0 R Link Detect
Port0/Port1 		Link detect status:
0: Cable link not detected.
1: Cable link detected.
If PORT1_SEL is set, this register is with reference to Port1.
13 0x0D GPIO0 Configuration 7:4 R Revision ID Revision ID.
3 RW 0x00 GPIO0 Output Value
D_GPIO0 Output Value 		Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH.
If PORT1_SEL is set, this register controls the D_GPIO0 pin.
2:0 RW GPIO0 ModeD_GPIO0 Mode Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE™
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss.
If PORT1_SEL is set, this register controls the D_GPIO0 pin.
14 0x0E GPIO1 and GPIO2 ConfigurationD_GPIO1 and D_GPIO2 Configuration 7 RW 0x00 GPIO2 Output ValueD_GPIO2 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH.
If PORT1_SEL is set, this register controls the D_GPIO2 pin.
6:4 RW GPIO2 ModeD_GPIO2 Mode Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE™.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss.
If PORT1_SEL is set, this register controls the D_GPIO2 pin.
3 RW GPIO1 Output ValueD_GPIO1 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH.
If PORT1_SEL is set, this register controls the D_GPIO1 pin.
2:0 RW GPIO1 ModeD_GPIO1 Mode Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE™.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss.
If PORT1_SEL is set, this register controls the D_GPIO1 pin.
15 0x0F GPIO3 ConfigurationD_GPIO3 Configuration 7:4 0x00 Reserved.
3 RW GPIO3 Output ValueD_GPIO3 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH.
If PORT1_SEL is set, this register controls the D_GPIO3 pin.
2:0 RW GPIO3 ModeD_GPIO3 Mode Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss.
If PORT1_SEL is set, this register controls the D_GPIO3 pin.
16 0x10 GPIO5_REG and GPIO6_REG Configuration 7 RW 0x00 GPIO6_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH.
6 Reserved.
5:4 RW GPIO6_REG Mode Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE™.
01: GPIO mode, output.
11: GPIO mode; input.
3 RW GPIO5_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH.
2 Reserved.
1:0 RW GPIO5_REG Mode Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE™.
01: GPIO mode, output.
11: GPIO mode; input.
17 0x11 GPIO7_REG and GPIO8_REG Configuration 7 RW 0x00 GPIO8_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH.
6 Reserved.
5:4 RW GPIO8_REG Mode Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE.
01: GPIO mode, output.
11: GPIO mode; input.
3 RW GPIO7_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH.
2 Reserved.
1:0 RW GPIO7_REG Mode Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE.
01: GPIO mode, output.
11: GPIO mode; input.
18 0x12 Data Path Control 7 0x00 Reserved.
6 RW Pass RGB Setting this bit causes RGB data to be sent independent of DE. However, setting this bit prevents HDCP operation and blocks packetized audio.
0: Normal operation.
1: Pass RGB independent of DE.
5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable) signal.
0: DE is positive (active high, idle low).
1: DE is inverted (active low, idle high).
4 RW I2S Repeater Regen Regenerate I2S data from Repeater I2S pins.
0: Repeater pass through I2S from video pins (default).
1: Repeater regenerate I2S from I2S pins.
3 RW I2S Channel B Enable Override I2S Channel B Enable Override.
0: Disable I2S Channel B override.
1: Set I2S Channel B Enable from 0x12[0].
2 RW 18-Bit Video Select 0: Select 24-bit video mode.
1: Select 18-bit video mode.
1 RW I2S Transport Select Select I2S transport mode:
0: Enable I2S Data Island transport (default).
1: Enable I2S Data Forward Channel Frame transport.
0 RW I2S Channel B Enable I2S Channel B Enable.
0: I2S Channel B disabled.
1: Enable I2S Channel B on B1 input.
Note that in a repeater, this bit may be overridden by the in-band I2S mode detection.
19 0x13 General Purpose Control 7 R 0x88 MODE_SEL1 Done Indicates MODE_SEL1 value has stabilized and has been latched.
6:4 R MODE_SEL1 Decode Returns the 3-bit decode of the MODE_SEL1 pin.
3 R MODE_SEL0 Done Indicates MODE_SEL0 value has stabilized and has been latched.
2:0 R MODE_SEL0 Decode Returns the 3-bit decode of the MODE_SEL0 pin.
20 0x14 BIST Control 7:3 0x00 Reserved.
2:1 RW OSC Clock Source Allows choosing different OSC clock frequencies for forward channel frame.

OSC clock frequency in functional mode when TMDS clock is not present and 0x03[2]=1:
00: 50 MHz oscillator.
01: 50 MHz oscillator.
10: 100 MHz oscillator.
11: 25 MHz oscillator.

Clock source in BIST mode i.e. when 0x14[0]=1:
00: External pixel clock.
01: 33 MHz oscillator.
1x: 100 MHz oscillator.
0 RW BIST Enable BIST control:
0: Disabled (default).
1: Enabled.
21 0x15 I2C Voltage Select 7:0 RW 0x01 I2C Voltage Select Selects 1.8 or 3.3V for the I2C_SDA and I2C_SCL pins. This register is loaded from the I2C_VSEL strap option from the SCLK pin at power-up. At power-up, a logic LOW will select 3.3V operation, while a logic HIGH (pull-up resistor attached) will select 1.8V signaling. Issuing either of the digital resets via register 0x01 will cause the I2C_VSEL value to be reset to 3.3V operation.
Reads of this register return the status of the I2C_VSEL control:
0: Select 1.8V signaling.
1: Select 3.3V signaling.
This bit may be overwritten via register access or via eFuse program by writing an 8-bit value to this register:
Write 0xb5 to set I2C_VSEL.
Write 0xb6 to clear I2C_VSEL.
22 0x16 BCC Watchdog Control 7:1 RW 0xFE Timer Value The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. Set to 0x01.
0 RW Timer Control Disable Bidirectional Control Channel (BCC) Watchdog Timer:
0: Enable BCC Watchdog Timer operation (default).
1: Disable BCC Watchdog Timer operation.
23 0x17 I2C Control 7 RW 0x1E I2C Pass All
Port0/Port1 		0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs matching either the remote Deserializer Slave ID or the remote Slave ID (default).
1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs that do not match the Serializer I2C Slave ID.
If PORT1_SEL is set, this bit controls Port1 operation.
6:4 RW SDA Hold Time Internal SDA hold time:
Configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 40 nanoseconds.
3:0 RW I2C Filter Depth Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 nanoseconds.
24 0x18 SCL High Time 7:0 RW 0x7F TX_SCL_HIGH I2C Master SCL high time:
This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the internal oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional oscillator clock periods.
Min_delay = 38.0952ns * (TX_SCL_HIGH + 5).
25 0x19 SCL Low Time 7:0 RW 0x7F TX_SCL_LOW I2C Master SCL low time:
This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the internal oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional clock periods.
Min_delay = 38.0952ns * (TX_SCL_LOW + 5).
26 0x1A Data Path Control 2 7:4 Reserved.
3 R Strap SECONDARY_AUDIO Enable Secondary Audio.
This register indicates that the AUX audio channel is enabled. The control for this function is via the AUX_AUDIO bit in the BRIDGE_CFG register register offset 0x54). The AUX_AUDIO control is strapped from the MODE_SEL0 pin at power-up.
2 0x01 Reserved.
1 RW MODE_28B Enable 28-bit Serializer Mode.
0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS).
1: 28-bit high-speed data mode.
0 RW I2S Surround Enable 5.1- or 7.1-channel I2S audio transport:
0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and 0.
1: 5.1- or 7.1-channel audio is enabled.

Note that I2S Data Island Transport is the only option for surround audio. Also note that in a repeater, this bit may be overridden by the in-band I2S mode detection (default).
27 0x1B BIST BC Error Count 7:0 R 0x00 BIST BC Error
Port0/Port1 		BIST back channel CRC error counter.
This register stores the back channel CRC error count during BIST Mode (saturates at 255 errors). Clears when a new BIST is initiated or by 0x04[5].
If PORT1_SEL is set, this register indicates Port1 status.
28 0x1C GPIO Pin Status 1 7 R 0x00 GPIO7_REG Pin Status GPIO7_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode.
6 R GPIO6_REG Pin Status GPIO6_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode.
5 R GPIO5_REG Pin Status GPIO5_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode.
4 Reserved.
3 R GPIO3 Pin Status
D_GPIO3 Pin Status 		GPIO3 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO3 input pin status.
2 R GPIO2 Pin Status
D_GPIO2 Pin Status 		GPIO2 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO2 input pin status.
1 R GPIO1 Pin Status
D_GPIO1 Pin Status 		GPIO1 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO1 input pin status.
0 R GPIO0 Pin Status
D_GPIO0 Pin Status 		GPIO0 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO0 input pin status.
29 0x1D GPIO Pin Status 2 7:1 0x00 Reserved
0 R GPIO8_REG Pin Status GPIO8_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode.
30 0x1E Transmitter Port Select 7:3 Reserved.
2 RW 0x01 PORT1_I2C_EN Port1 I2C Enable.
Enables secondary I2C address. The second I2C address provides access to Port1 registers as well as registers that are shared between Port0 and Port1. The second I2C address value will be set to DeviceID + 1 (7-bit format). The PORT1_I2C_EN bit must also be set to allow accessing remote devices over the second link when the device is in Replicate mode.
1 RW PORT1_SEL Selects Port1 for register access from primary I2C address.
For writes, Port1 registers and shared registers will both be written.
For reads, Port1 registers and shared registers will be read. This bit must be cleared to read Port0 registers.
This bit is ignored if PORT1_I2C_EN is set.
0 RW PORT0_SEL Selects Port0 for register access from primary I2C address.
For writes, Port0 registers and shared registers will both be written.
For reads, Port0 registers and shared registers will be read. Note that if PORT1_SEL is also set, then Port1 registers will be read.
This bit is ignored if PORT1_I2C_EN is set.
31 0x1F Frequency Counter 7:0 RW 0x00 Frequency Count Frequency counter control.
A write to this register will enable a frequency counter to count the number of pixel clock during a specified time interval. The time interval is equal to the value written multiplied by the oscillator clock period (nominally 40ns). A read of the register returns the number of pixel clock edges seen during the enabled interval. The frequency counter will freeze at 0xff if it reaches the maximum value. The frequency counter will provide a rough estimate of the pixel clock period. If the pixel clock frequency is known, the frequency counter may be used to determine the actual oscillator clock frequency.
32 0x20 Deserializer Capabilities 1 7 RW 0x00 FREEZE_DES_CAP
Port0/Port1 		Freeze Deserializer Capabilities.
Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel. The Capabilities will be frozen at the values written in registers 0x20 and 0x21.
If PORT1_SEL is set, this register indicates Port1 capabilities.
6 0x00 HSCC_MODE[0]
Port0/Port1 		High-Speed Control Channel bit 0.
Lowest bit of the 3-bit HSCC indication. The other 2 bits are contained in Deserializer Capabilities 2. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
5 SEND_FREQ
Port0/Port1 		Send Frequency Training Pattern.
Indicates the DS90UH949-Q1 should send the Frequency Training Pattern. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
4 RW 0x00 SEND_EQ
Port0/Port1 		Send Equalization Training Pattern.
Indicates the DS90UH949-Q1 should send the Equalization Training Pattern. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
3 RW DUAL_LINK_CAP
Port0/Port1 		Dual link Capabilities.
Indicates if the Deserializer is capable of dual link operation. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
2 RW DUAL_CHANNEL
Port0/Port1 		Dual Channel 0/1 Indication.
In a dual-link capable device, indicates if this is the primary or secondary channel.
0: Primary channel (channel 0).
1: Secondary channel (channel 1).
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
32 0x20 Deserializer Capabilities 1 1 RW 0x00 VID_24B_HD_AUD
Port0/Port1 		Deserializer supports 24-bit video concurrently with HD audio.
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
0 RW DES_CAP_FC_GPIO
Port0/Port1 		Deserializer supports GPIO in the Forward Channel Frame.
This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this register indicates Port1 capabilities.
33 0x21 Deserializer Capabilities 2 7:2 Reserved.
1:0 RW 0x00 HSCC_MODE[2:1]
Port0/Port1 		High-Speed Control Channel bits [2:1].
Upper bits of the 3-bit HSCC indication. The lowest bit is contained in Deserializer Capabilities 1.
000: Normal back channel frame, GPIO mode.
001: High Speed GPIO mode, 1 GPIO.
010: High Speed GPIO mode, 2 GPIOs.
011: High Speed GPIO mode: 4 GPIOs.
100: Reserved.
101: Reserved.
110: High Speed, Forward Channel SPI mode.
111: High Speed, Reverse Channel SPI mode. In Single Link devices, only Normal back channel frame modes are supported.
If PORT1_SEL is set, this register indicates Port1 capabilities.
38 0x26 Link Detect Control 7:3 Reserved.
2:0 RW 0x00 LINK DETECT TIMER Bidirectional Control Channel Link Detect Timer.
This field configures the link detection timeout period. If the timer expires without valid communication over the reverse channel, link detect will be deasserted.
000: 162 microseconds.
001: 325 microseconds.
010: 650 microseconds.
011: 1.3 milliseconds.
100: 10.25 microseconds.
101: 20.5 microseconds.
110: 41 microseconds.
111: 82 microseconds.
48 0x30 SCLK_CTRL 7 RW 0x00 SCLK/WS SCLK to Word Select Ratio.
0 : 64.
1 : 32.
6:5 RW MCLK/SCLK MCLK to SCLK Select Ratio.
00 : 4.
01 : 2.
10 : 1.
11 : 8.
4:3 RW CLEAN CLOCK_DIV Clock Cleaner divider.
00 : FPD_VCO_CLOCK/8.
01 : FPD_VCO_CLOCK/4.
10 : FPD_VCO_CLOCK/2.
11 : AON_OSC.
2:1 RW CLEAN Mode If non-zero, the SCLK Input or HDMI N/CTS generated Audio Clock is cleaned digitally before being used.
00 : Off.
01 : ratio of 1.
10 : ratio of 2.
11 : ratio of 4.
0 RW MASTER If set, the SCLK I/O and the WS_IO are used as an output and the Clock Generation Circuits are enabled, otherwise they are inputs.
49 0x31 AUDIO_CTS0 7:0 RW 0x00 CTS[7:0] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
50 0x32 AUDIO_CTS1 7:0 RW 0x00 CTS[15:8] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
51 0x33 AUDIO_CTS2 7:0 RW 0x00 CTS[23:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
52 0x34 AUDIO_N0 7:0 RW 0x00 N[7:0] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
53 0x35 AUDIO_N1 7:0 RW 0x00 N[15:8] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
54 0x36 AUDIO_N2_COEFF 7:4 RW 0x00 COEFF[3:0] Selects the LPF_COEFF in the Clock Cleaner (Feedback is divided by 2^COEFF).
3:0 RW 0x00 N[19:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.
55 0x37 CLK_CLEAN_STS 7:6 Reserved.
5:3 R 0x00 IN_FIFO_LVL Clock Cleaner Input FIFO Level.
2:0 R 0x00 OUT_FIFO_LVL Clock Cleaner Output FIFO Level.
64 0x40 ANA_IA_CNTL 7:5 0x00 Reserved.
4:2 RW ANA_IA_SEL Analog register select
Selects target for register access
000b: Disabled
001b - 011b: Reserved
100b: HDMI Registers
101b: FPD3 TX Registers
11xb: Reserved
1 RW ANA_AUTO_INC Analog Register Auto Increment
0: Disable auto-increment mode
1: Enable auto-increment mode. Upon completion of a read or write, the register address will automatically be incremented by 1.
0 RW ANA_IA_READ Start Analog Register Read
0: Write analog register
1: Read analog register
65 0x41 ANA_IA_ADDR 7:0 RW 0x00 ANA_IA_ADDR Analog register offset
This register contains the 8-bit register offset for the indirect access.
66 0x42 ANA_IA_DATA 7:0 RW 0x00 ANA_IA_DATA Analog register data
Writing this register will cause an indirect write of the ANA_IA_DATA value to the selected analog block register. Reading this register will return the value of the selected analog block register.
72 0x48 APB_CTL 7:5 Reserved.
4:3 RW 0x00 APB_SELECT APB Select: Selects target for register access.
00 : HDMI APB interface.
01 : EDID SRAM.
10 : Configuration Data (read only).
11 : Die ID (read only).
2 RW APB_AUTO_INC APB Auto Increment: Enables auto-increment mode. Upon completion of an APB read or write, the APB address will automatically be incremented by 0x4 for HDMI registers or by 0x1 for others.
1 RW APB_READ Start APB Read: Setting this bit to a 1 will begin an APB read. Read data will be available in the APB_DATAx registers. The APB_ADRx registers should be programmed prior to setting this bit. This bit will be cleared when the read is complete.
0 RW APB_ENABLE APB Interface Enable: Set to a 1 to enable the APB interface. The APB_SELECT bits indicate what device is selected.
73 0x49 APB_ADR0 7:0 RW 0x00 APB_ADR0 APB Address byte 0 (LSB).
74 0x4A APB_ADR1 7:0 RW 0x00 APB_ADR1 APB Address byte 1 (MSB).
75 0x4B APB_DATA0 7:0 RW 0x00 APB_DATA0 Byte 0 (LSB) of the APB Interface Data.
76 0x4C APB_DATA1 7:0 RW 0x00 APB_DATA1 Byte 1 of the APB Interface Data.
77 0x4D APB_DATA2 7:0 RW 0x00 APB_DATA2 Byte 2 of the APB Interface Data.
78 0x4E APB_DATA3 7:0 RW 0x00 APB_DATA3 Byte 3 (MSB) of the APB Interface Data.
79 0x4F BRIDGE_CTL 7:5 Reserved.
4 RW 0x00 CEC_CLK_SRC CEC Clock Source Select: Selects clock source for generating the 32.768kHz clock for CEC operations in the HDMI Receive Controller.
0 : Selects internal generated clock.
1 : Selects external 25MHz oscillator clock.
3 RW CEC_CLK_EN CEC Clock Enable: Enable CEC clock generation. Enables generation of the 32.768kHz clock for the HDMI Receive controller. This bit should be set prior to enabling CEC operation via the HDMI controller registers.
2 RW EDID_CLEAR Clear EDID SRAM: Set to 1 to enable clearing the EDID SRAM. The EDID_INIT bit must be set at the same time for the clear to occur. This bit will be cleared when the initialization is complete.
1 RW EDID_INIT Initialize EDID SRAM from EEPROM: Causes a reload of the EDID SRAM from the non-volatile EDID EEPROM. This bit will be cleared when the initialization is complete.
0 R Strap EDID_DISABLE Disable EDID access via DDC/I2C: Disables access to the EDID SRAM via the HDMI DDC interface. This value is loaded from the MODE_SEL0 pin at power-up.
80 0x50 BRIDGE_STS 7 R 0x03 RX5V_DETECT RX +5V detect: Indicates status of the RX_5V pin. When asserted, indicates the HDMI interface has detected valid voltage on the RX_5V input.
6 R HDMI_INT HDMI Interrupt Status: Indicates an HDMI Interrupt is pending. HDMI interrupts are serviced through the HDMI Registers via the APB Interface.
5 R HDCP_INT HDCP Interrupt Status: Indicates an HDCP Transmitter Interrupt is pending. HDCP Transmit interrupts are serviced through the HDCP Interrupt Control and Status registers.
4 R INIT_DONE Initialization Done: Initialization sequence has completed. This step will complete after configuration complete (CFG_DONE).
3 R REM_EDID_LOAD Remote EDID Loaded: Indicates EDID SRAM has been loaded from a remote EDID EEPROM device over the Bidirectional Control Channel. The EDID_CKSUM value indicates if the EDID load was successful.
2 R CFG_DONE Configuration Complete: Indicates automatic configuration has completed. This step will complete prior to initialization complete (INIT_DONE).
1 R CFG_CKSUM Configuration checksum status: Indicates result of Configuration checksum during initialization. The device verifies the 2’s complement checksum in the last 128 bytes of the EEPROM. A value of 1 indicates the checksum passed.
0 R EDID_CKSUM EDID checksum Status: Indicates result of EDID checksum during EDID initialization. The device verifies the 2’s complement checksum in the first 256 bytes of the EEPROM. A value of 1 indicates the checksum passed.
81 0x51 EDID_ID 7:1 RW 0x50 EDID_ID EDID I2C Slave Address: I2C address used for accessing the EDID information. These are the upper 7 bits in 8-bit format addressing, where the lowest bit is the Read/Write control.
0 RW 0 EDID_RDONLY EDID Read Only: Set to a 1 puts the EDID SRAM memory in read-only mode for access via the HDMI DDC interface. Setting to a 0 allows writes to the EDID SRAM memory.
82 0x52 EDID_CFG0 7 Reserved.
6:4 RW 0x01 EDID_SDA_HOLD Internal SDA Hold Time: This field configures the amount of internal hold time provided for the DDC_SDA input relative to the DDC_SCL input. Units are 40 nanoseconds. The hold time is used to qualify the start detection to avoid false detection of Start or Stop conditions.
3:0 RW 0x0E EDID_FLTR_DPTH I2C Glitch Filter Depth: This field configures the maximum width of glitch pulses on the DDC_SCL and DDC_SDA inputs that will be rejected. Units are 5 nanoseconds.
83 0x53 EDID_CFG1 7:2 Reserved.
1:0 RW 0x00 EDID_SDA_DLY SDA Output Delay: This field configures output delay on the DDC_SDA output when the EDID memory is accessed. Setting this value will increase output delay in units of 40ns. Nominal output delay values for DDC_SCL to DDC_SDA are:
00 : 240ns.
01 : 280ns.
10 : 320ns.
11 : 360ns.
84 0x54 BRIDGE_CFG 7 RW Strap EXT_CTL External Control: When this bit Is set, the internal bridge control function is disabled. This disables initialization of the HDMI Receiver as well as initiation of HDCP functions. These operations must be controlled by an external controller attached to the I2C interface. This value is loaded from the MODE_SEL1 pin at power-up.
6 RW 0x00 HDMI_INT_EN HDMI Interrupt Enable: When this bit is set, Interrupts from the HDMI Receive controller will be reported on the INTB pin. Software may check the BRIDGE_STS register to determine if the interrupt is from the HDMI Receiver or the HDCP Transmitter.
5 RW Strap DIS_REM_EDID Disable Remote EDID load: Disables automatic load of EDID SRAM from a remote EDID EEPROM. By default, the device will check the remote I2C bus for an EEPROM with a valid EDID, and load the EDID data to local EDID SRAM. If this bit is set to a 1, the remote EDID load will be bypassed. This value is loaded from the MODE_SEL1 pin at power-up.
4 RW 0x00 AUTO_INIT_DIS Disable Automatic initialization: The Bridge control will automatically initialize the HDMI Receiver for operation. Setting this bit to a 1 will disable automatic initialization of the HDMI Receiver. In this mode, initialization of the HDMI Receiver must be done through EEPROM configuration or via external control.
3 RW 0x00 AUTO_HDCP_DIS Disable Automatic HDCP_CTRL setting: By default the internal bridge control function will configure the HDMI Receiver for HDCP operation using default settings for bits in the HDCP_CTRL register. Setting this bit to a 1 will disable automatic control of the HDCP_CTRL register in the HDMI Receiver.
2 RW 0x00 AUDIO_TDM Enable TDM Audio: Setting this bit to a 1 will enable TDM audio for the HDMI audio.
1 RW AUDIO_MODE Audio Mode: Selects source for audio to be sent over the FPD-Link III downstream link.
0 : HDMI audio.
1 : Local/DVI audio.
Local audio is sourced from the device I2S pins rather than from HDMI, and is useful in modes such as DVI that do not include audio.
0 RW Strap AUX_AUDIO_EN AUX Audio Channel Enable: Setting this bit to a 1 will enable the AUX audio channel. This allows sending additional 2-channel audio in addition to the HDMI or DVI audio. This bit is loaded from the MODE_SEL0 pin at power-up.
85 0x55 AUDIO_CFG 7 RW 0x00 TDM_2_PARALLEL Enable I2S TDM to parallel audio conversion: When this bit is set, the i2s tdm to parallel conversion module is enabled. The clock output from the i2s tdm to parallel conversion module is them used to send data to the deserializer.
6 RW HDMI_I2S_OUT HDMI Audio Output Enable: When this bit is set, the HDMI I2S audio data will be output on the I2S audio interface pins. This control is ignored if the BRIDGE_CFG:AUDIO_MODE is not set to 00 (HDMI audio only).
5:4 Reserved.
3 RW 0x0C RST_ON_TYPE Reset Audio FIFO on Type Change: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio type.
2 RW RST_ON_AIF Reset Audio FIFO on Audio Infoframe: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio Infoframe checksum.
1 RW RST_ON_AVI Reset Audio FIFO on Audio Video Information Infoframe: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio Video Information Infoframe checksum.
0 RW RST_ON_ACR Reset Audio FIFO on Audio Control Frame: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio Control Frame N or CTS fields.
90 0x5A DUAL_STS 7 R 0x00 FPD3_LINK_RDY This bit indicates that the FPD-Link III has detected a valid downstream connection and determined capabilities for the downstream link.
6 R FPD3_TX_STS FPD-Link III transmit status:
This bit indicates that the FPD-Link III transmitter is active and the receiver is LOCKED to the transmit clock. It is only asserted once a valid input has been detected, and the FPD-Link III transmit connection has entered the correct mode (Single vs. Dual mode).
5:4 R FPD3_PORT_STS FPD3 Port Status: If FPD3_TX_STS is set to a 1, this field indicates the port mode status as follows:
00: Dual FPD-Link III Transmitter mode.
01: Single FPD-Link III Transmit on port 0.
10: Single FPD-Link III Transmit on port 1.
11: Replicate FPD-Link III Transmit on both ports.
3 R TMDS_VALID HDMI TMDS Valid: This bit indicates the TMDS interface is recovering valid TMDS data from HDMI.
2 R HDMI_PLL_LOCK HDMI PLL lock status: Indicates the HDMI PLL has locked to the incoming TMDS clock.
1 R NO_HDMI_CLK No TMDS Clock Detected: This bit indicates the Frequency Detect circuit did not detect an TMDS clock greater than the value specified in the FREQ_LOW register.
0 R FREQ_STABLE HDMI Frequency is Stable: Indicates the Frequency Detection circuit has detected a stable TMDS clock frequency.
91 0x5B DUAL_CTL1 7 RW Strap FPD3_COAX_MODE FPD3 Coax Mode: Enables configuration for the FPD3 Interface cabling type.
0 : Twisted Pair.
1 : Coax This bit is loaded from the MODE_SEL1 pin at power-up.
6 RW 0 DUAL_SWAP Dual Swap Control: Indicates current status of the Dual Swap control. If automatic correction of Dual Swap is disabled via the DISABLE_DUAL_SWAP control, this bit may be modified by software.
5 RW 1 RST_PLL_FREQ Reset FPD3 PLL on Frequency Change: When set to a 1, frequency changes detected by the Frequency Detect circuit will result in a reset of the FPD3 PLL. Set to 0.
4 RW 0 FREQ_DET_PLL Frequency Detect Select PLL Clock: Determines the clock source for the Frequency detection circuit:
0 : TMDS clock (prior to PLL).
1: HDMI PLL clock.
3 RW 0 DUAL_ALIGN_DE Dual align on DE (valid in dual-link mode):
0: Data will be sent on alternating links without regard to odd/even pixel position.
1: Odd/Even data will be sent on the primary/secondary links, respectively, based on the assertion of DE.
2 RW 0 DISABLE_DUAL Disable Dual Mode: During Auto-detect operation, setting this bit to a 1 will disable Dual FPD-Link III operation.
0: Normal Auto-detect operation.
1: Only Single or Replicate operation supported.
This bit will have no effect if FORCE_LINK is set.
1 RW 0 FORCE_DUAL Force dual mode:
When FORCE_LINK bit is set, the value on this bit controls single versus dual operation:
0: Single FPD-Link III Transmitter mode.
1: Dual FPD-Link III Transmitter mode.
0 RW 0 FORCE_LINK Force Link Mode: Forces link to dual or single mode, based on the FORCE_DUAL control setting. If this bit is 0, mode setting will be automatically set based on downstream device capabilities as well as the incoming data frequency.
0 : Auto-Detect FPD-Link III mode.
1 : Forced Single or Dual FPD-Link III mode.
92 0x5C DUAL_CTL2 7 RW 0 DISABLE_DUAL_SWAP Disable Dual Swap: Prevents automatic correction of swapped Dual link connection. Setting this bit allows writes to the DUAL_SWAP control in the DUAL_CTL1 register.
6 RW 0x00 FORCE_LINK_RDY Force Link Ready: Forces link ready indication, bypassing back channel link detection.
5 RW FORCE_CLK_DET Force Clock Detect: Forces the HDMI/OpenLDI clock detect circuit to indicate presence of a valid input clock. This bypasses the clock detect circuit, allowing operation with an input clock that does not meet frequency or stability requirements.
4:3 RW FREQ_STBL_THR Frequency Stability Threshold: The Frequency detect circuit can be used to detect a stable clock frequency. The Stability Threshold determines the amount of time required for the clock frequency to stay within the FREQ_HYST range to be considered stable:
00 : 40us.
01 : 80us.
10 : 320us.
11 : 1.28ms.
2:0 RW 0x02 FREQ_HYST Frequency Detect Hysteresis: The Frequency detect hysteresis setting allows ignoring minor fluctuations in frequency. A new frequency measurement will be captured only if the measured frequency differs from the current measured frequency by more than the FREQ_HYST setting. The FREQ_HYST setting is in MHz.
93 0x5D FREQ_LOW 7 Reserved.
6 RW 0 HDMI_RST_MODE HDMI Phy Reset Mode:
0 : Reset HDMI Phy on change in mode or frequency.
1 : Don't reset HDMI Phy on change in mode or frequency if +5 V is asserted.
5:0 RW 6 FREQ_LO_THR Frequency Low Threshold: Sets the low threshold for the TMDS Clock frequency detect circuit in MHz. This value is used to determine if the TMDS clock frequency is too low for proper operation.
94 0x5E FREQ_HIGH 7 Reserved.
6:0 RW 44 FREQ_HI_THR Frequency High Threshold: Sets the high threshold for the TMDS Clock frequency detect circuit in MHz.
95 0x5F HDMI Frequency 7:0 R 0x00 HDMI_FREQ HDMI frequency:
Returns the value of the HDMI frequency in MHz. A value of 0 indicates the HDMI receiver is not detecting a valid signal.
96 0x60 SPI_TIMING1 7:4 RW 0x02 SPI_HOLD SPI Data Hold from SPI clock: These bits set the minimum hold time for SPI data following the SPI clock sampling edge. In addition, this also sets the minimum active pulse width for the SPI output clock.
0: Do not use.
0x1-0xF: Hold = (SPI_HOLD + 1) * 40ns.
For example, default setting of 2 will result in 120ns data hold time.
3:0 RW 0x02 SPI_SETUP SPI Data Setup to SPI Clock: These bits set the minimum setup time for SPI data to the SPI clock active edge. In addition, this also sets the minimum inactive width for the SPI output clock.
0: Do not use.
0x1-0xF: Hold = (SPI_SETUP + 1) * 40ns.
For example, default setting of 2 will result in 120ns data setup time.
97 0x61 SPI_TIMING2 7:4 Reserved.
3:0 RW 0x00 SPI_SS_SETUP SPI Slave Select Setup: This field controls the delay from assertion of the Slave Select low to initial data timing. Delays are in units of 40ns.
Delay = (SPI_SS_SETUP + 1) * 40ns.
98 0x62 SPI_CONFIG 7:2 Reserved.
1 R 0x00 SPI_CPHA SPI Clock Phase setting: Determines which phase of the SPI clock is used for sampling data.
0: Data sampled on leading (first) clock edge.
1: Data sampled on trailing (second) clock edge.
This bit is read-only, with a value of 0. There is no support for CPHA of 1.
0 RW SPI_CPOL SPI Clock Polarity setting: Determines the base (inactive) value of the SPI clock.
0: base value of the clock is 0.
1: base value of the clock is 1.
This bit affects both capture and propagation of SPI signals.
100 0x64 Pattern Generator Control 7:4 RW 0x10 Pattern Generator Select Fixed Pattern Select
Selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled.
xxxx: normal/inverted.
0000: Checkerboard.
0001: White/Black (default).
0010: Black/White.
0011: Red/Cyan.
0100: Green/Magenta.
0101: Blue/Yellow.
0110: Horizontal Black-White/White-Black.
0111: Horizontal Black-Red/White-Cyan.
1000: Horizontal Black-Green/White-Magenta.
1001: Horizontal Black-Blue/White-Yellow.
1010: Vertical Black-White/White-Black.
1011: Vertical Black-Red/White-Cyan.
1100: Vertical Black-Green/White-Magenta.
1101: Vertical Black-Blue/White-Yellow.
1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers.
1111: VCOM.
See TI App Note AN-2198.
3 Reserved.
2 RW Color Bars Pattern Enable color bars:
0: Color Bars disabled (default).
1: Color Bars enabled.
Overrides the selection from reg_0x64[7:4].
1 RW VCOM Pattern Reverse Reverse order of color bands in VCOM pattern:
0: Color sequence from top left is (YCBR) (default).
1: Color sequence from top left is (RBCY).
0 RW Pattern Generator Enable Pattern Generator enable:
0: Disable Pattern Generator (default).
1: Enable Pattern Generator.
101 0x65 Pattern Generator Configuration 7 0x00 Reserved.
6 RW Checkerboard Scale Scale Checkered Patterns:
0: Normal operation (each square is 1x1 pixel) (default).
1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels).
Setting this bit gives better visibility of the checkered patterns.
5 RW Custom Checkerboard Use Custom Checkerboard Color:
0: Use white and black in the Checkerboard pattern (default).
1: Use the Custom Color and black in the Checkerboard pattern.
4 RW PG 18–bit Mode 18-bit Mode Select:
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness (default).
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits.
3 RW External Clock Select External Clock Source:
0: Selects the internal divided clock when using internal timing (default).
1: Selects the external pixel clock when using internal timing.
This bit has no effect in external timing mode (PATGEN_TSEL = 0).
2 RW Timing Select Timing Select Control:
0: The Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals (default).
1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.
See Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132).
1 RW Color Invert Enable Inverted Color Patterns:
0: Do not invert the color output (default).
1: Invert the color output.
See Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132).
0 RW Auto Scroll Auto Scroll Enable:
0: The Pattern Generator retains the current pattern (default).
1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register.
See Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132).
102 0x66 PGIA 7:0 RW 0x00 PG Indirect Address This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register.
See Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132).
103 0x67 PGID 7:0 RW 0x00 PG Indirect Data When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value.
See Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132).
112 0x70 Slave ID[1] 7:1 RW 0x00 Slave ID 1
Port0/Port1 		7-bit I2C address of the remote Slave 1 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 1.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
113 0x71 Slave ID[2] 7:1 RW 0x00 Slave ID 2
Port0/Port1 		7-bit I2C address of the remote Slave 2 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 2.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
114 0x72 Slave ID[3] 7:1 RW 0x00 Slave ID 3
Port0/Port1 		7-bit I2C address of the remote Slave 3 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 3.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
115 0x73 Slave ID[4] 7:1 RW 0x00 Slave ID 4
Port0/Port1 		7-bit I2C address of the remote Slave 4 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 4.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
116 0x74 Slave ID[5] 7:1 RW 0x00 Slave ID 5
Port0/Port1 		7-bit I2C address of the remote Slave 5 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 5.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
117 0x75 Slave ID[6] 7:1 RW 0x00 Slave ID 6
Port0/Port1 		7-bit I2C address of the remote Slave 6 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 6.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
118 0x76 Slave ID[7] 7:1 RW 0x00 Slave ID 7
Port0/Port1 		7-bit I2C address of the remote Slave 7 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 7.
If PORT1_SEL is set, this register controls Port 1 Slave ID.
0 Reserved.
119 0x77 Slave Alias[1] 7:1 RW 0x00 Slave Alias ID 1
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 1 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 1 register. A value of 0 in this field disables access to the remote Slave 1.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
120 0x78 Slave Alias[2] 7:1 RW 0x00 Slave Alias ID 2
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 2 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 2 register. A value of 0 in this field disables access to the remote Slave 2.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
121 0x79 Slave Alias[3] 7:1 RW 0x00 Slave Alias ID 3
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 3 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 3 register. A value of 0 in this field disables access to the remote Slave 3.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
122 0x7A Slave Alias[4] 7:1 RW 0x00 Slave Alias ID 4
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 4 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 4 register. A value of 0 in this field disables access to the remote Slave 4.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
123 0x7B Slave Alias[5] 7:1 RW 0x00 Slave Alias ID 5
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 5 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 5 register. A value of 0 in this field disables access to the remote Slave 5.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
124 0x7C Slave Alias[6] 7:1 RW 0x00 Slave Alias ID 6
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 6 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 6 register. A value of 0 in this field disables access to the remote Slave 6.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
125 0x7D Slave Alias[7] 7:1 RW 0x00 Slave Alias ID 7
Port0/Port1 		7-bit Slave Alias ID of the remote Slave 7 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 7 register. A value of 0 in this field disables access to the remote Slave 7.
If PORT1_SEL is set, this register controls Port 1 Slave Alias.
0 Reserved.
128 0x80 RX_BKSV0 7:0 R 0x00 RX_BKSV0 BKSV0: Value of byte0 of the Receiver KSV.
129 0x81 RX_BKSV1 7:0 R 0x00 RX_BKSV1 BKSV1: Value of byte1 of the Receiver KSV.
130 0x82 RX_BKSV2 7:0 R 0x00 RX_BKSV2 BKSV2: Value of byte2 of the Receiver KSV.
131 0x83 RX_BKSV3 7:0 R 0x00 RX_BKSV3 BKSV3: Value of byte3 of the Receiver KSV.
132 0x84 RX_BKSV4 7:0 R 0x00 RX_BKSV4 BKSV4: Value of byte4 of the Receiver KSV.
144 0x90 TX_KSV0 7:0 R 0x00 TX_KSV0 TX_KSV0: Value of byte0 of the Transmitter KSV.
145 0x91 TX_KSV1 7:0 R 0x00 TX_KSV1 TX_KSV1: Value of byte1 of the Transmitter KSV.
146 0x92 TX_KSV2 7:0 R 0x00 TX_KSV2 TX_KSV2: Value of byte2 of the Transmitter KSV.
147 0x93 TX_KSV3 7:0 R 0x00 TX_KSV3 TX_KSV3: Value of byte3 of the Transmitter KSV.
148 0x94 TX_KSV4 7:0 R 0x00 TX_KSV4 TX_KSV4: Value of byte4 of the Transmitter KSV.
160 0xA0 RX_BCAPS 7 Reserved.
6 R 0x01 Repeater Repeater: Indicates if the attached Receiver supports downstream connections. This bit is valid once the Bksv is ready as indicated by the BKSV_RDY bit in the HDCP.
5 R KSV_FIFO_RDY KSV FIFO Ready: Indicates the receiver has built the list of attached KSVs and computed the verification value V’.
4 R FAST_I2C Fast I2C: The HDCP Receiver supports fast I2C. Since the I2C is embedded in the serial data, this bit is not relevant.
3:2 Reserved.
1 R 0x03 FEATURES_1_1 1.1_Features: The HDCP Receiver supports the Enhanced Encryption Status Signaling (EESS), Advance Cipher, and Enhanced Link Verification options.
0 R FAST_REAUTH Fast Reauthentication: The HDCP Receiver is capable of receiving (unencrypted) video signal during the session re-authentication.
161 0xA1 RX_BSTATUS0 7 R 0x00 MAX_DEVS_EXCEEDED Maximum Devices Exceeded: Indicates a topology error was detected. Indicates the number of downstream devices has exceeded the depth of the Repeater's KSV FIFO.
6:0 R DEVICE_COUNT Device Count: Total number of attached downstream device. For a Repeater, this will indicate the number of downstream devices, not including the Repeater. For an HDCP Receiver that is not also a Repeater, this field will be 0.
162 0xA2 RX_BSTATUS1 7:4 Reserved.
3 R 0x00 MAX_CASC_EXCEEDED Maximum Cascade Exceeded: Indicates a topology error was detected. Indicates that more than seven levels of repeaters have been cascaded together.
2:0 R Cascade Depth Cascade Depth: Indicates the number of attached levels of devices for the Repeater.
163 0xA3 KSV_FIFO 7:0 R 0x00 KSV_FIFO KSV FIFO: Each read of the KSV FIFO returns one byte of the KSV FIFO list composed by the downstream Receiver.
192 0xC0 HDCP_DBG 7 Reserved.
6 RW 0x00 HDCP_I2C_TO_DIS HDCP I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout function in the HDCP I2C master. When enabled, the bus timeout function allows the I2C master to assume the bus is free if no signaling occurs for more than 1 second.
5 Reserved.
4 RW 0x00 DIS_RI_SYNC Disable Ri Synchronization check: Ri is normally checked both before and after the start of frame 128. The check at frame 127 ensures synchronization between the two. Setting this bit to a 1 will disable the check at frame 127.
3 RW RGB_CHKSUM_EN Enable RBG video line checksum: Enables sending of ones-complement checksum for each 8-bit RBG data channel following end of each video data line.
2 RW FC_TESTMODE Frame Counter Test mode: Speeds up frame counter used for Pj and Ri verification. When set to a 1, Pj is computed every 2 frames and Ri is computed every 16 frames. When set to a 0, Pj is computed every 16 frames and Ri is computed every 128 frames.
1 RW TMR_SPEEDUP Timer Speedup: Speed up HDCP authentication timers.
0 RW HDCP_I2C_FAST HDCP I2C Fast Mode Enable Setting this bit to a 1 will enable the HDCP I2C Master in the HDCP Receiver to operation with Fast mode timing. If set to a 0, the I2C Master will operation with Standard mode timing. This bit is mirrored in the IND_STS register.
194 0xC2 HDCP_CFG 7 RW 0xA8 ENH_LV Enable Enhanced Link Verification: Enables enhanced link verification. Allows checking of the encryption Pj value on every 16th frame.
0 = Enhanced Link Verification disabled.
1 = Enhanced Link Verification enabled.
6 RW HDCP_EESS Enable Enhanced Encryption Status Signaling: Enables Enhanced Encryption Status Signaling (EESS) instead of the Original Encryption Status Signaling (OESS).
0 = OESS mode enabled.
1 = EESS mode enabled.
5 RW TX_RPTR Transmit Repeater Enable: Enables the transmitter to act as a repeater. In this mode, the HDCP Transmitter incorporates the additional authentication steps required of an HDCP Repeater.
0 = Transmit Repeater mode disabled.
1 = Transmit Repeater mode enabled.
4:3 RW ENC_MODE Encryption Control Mode: Determines mode for controlling whether encryption is required for video frames.
00 = Enc_Authenticated.
01 = Enc_Reg_Control.
10 = Enc_Always.
11 = Enc_InBand_Control (per frame).
2 RW WAIT_100MS Enable 100MS Wait: The HDCP 1.3 specification allows for a 100Ms wait to allow the HDCP Receiver to compute the initial encryption values. The FPD-Link III implementation guarantees that the Receiver will complete the computations before the HDCP Transmitter. Thus the timer is unnecessary. To enable the 100ms timer, set this bit to a 1.
1 RW RX_DET_SEL RX Detect Select: Controls assertion of the Receiver Detect Interrupt. If set to 0, the Receiver Detect Interrupt will be asserted on detection of an FPD-Link III Receiver. If set to 1, the Receiver Detect Interrupt will also require a receive lock indication from the receiver.
0 RW HDCP_AVMUTE Enable AVMUTE: Setting this bit to a 1 will initiate AVMUTE operation. The transmitter will ignore encryption status controls while in this state. If this bit is set to a 0, normal operation will resume. This bit may only be set if the HDCP_EESS bit is also set.
195 0xC3 HDCP_CTL 7 RW 0x00 HDCP_RST HDCP Reset : Setting this bit will reset the HDCP transmitter and dis-able HDCP authentication. This bit is self-clearing.
6 Reserved.
5 RW 0x00 KSV_LIST_VALID KSV List Valid : The controller sets this bit after validating the Repeater’s KSV List against the Key revocation list. This allows completion of the Authentication process. This bit is self-clearing.
4 RW KSV_VALID KSV Valid : The controller sets this bit after validating the Receiver’s KSV against the Key revocation list. This allows continuation of the Authentication process. This bit will be cleared upon assertion of the KSV_RDY flag in the HDCP_STS register. Setting this bit to a 0 will have no effect.
3 RW HDCP_ENC_DIS HDCP Encrypt Disable : Disables HDCP encryption. Setting this bit to a 1 will cause video data to be sent without encryption. Authentication status will be maintained. This bit is self-clearing.
2 RW HDCP_ENC_EN HDCP Encrypt Enable : Enables HDCP encryption. When set, if the device is authenticated, encrypted data will be sent. If device is not authenticated, a blue screen will be sent. Encryption should always be enabled when video data requiring content protection is being supplied to the transmitter. When this bit is not set, video data will be sent without encryption. Note that when CFG_ENC_MODE is set to Enc_Always, this bit will be read only with a value of 1.
1 RW HDCP_DIS HDCP Disable: Disables HDCP authentication. Setting this bit to a 1 will disable the HDCP authentication. This bit is self-clearing.
0 RW HDCP_EN HDCP Enable/Restart: Enables HDCP authentication. If HDCP is already enabled, setting this bit to a 1 will restart authentication. Setting this bit to a 0 will have no effect. A register read will return the current HDCP enabled status.
196 0xC4 HDCP_STS 7 R 0x00 I2C_ERR_DET HDCP I2C Error Detected: This bit indicates an error was detected on the embedded communications channel with the HDCP Receiver. Setting of this bit might indicate that a problem exists on the link between the HDCP Transmitter and HDCP Receiver. This bit will be cleared on read.
6 R RX_INT RX Interrupt : Status of the RX Interrupt signal. The signal is received from the attached HDCP Receiver and is the status on the INTB_IN pin of the HDCP Receiver. The signal is active low, so a 0 indicates an interrupt condition.
5 R RX_LOCK_DET Receiver Lock Detect : This bit indicates that the downstream Receiver has indicated Receive Lock to incoming serial data.
4 R DOWN_HPD Downstream Hot Plug Detect: This bit indicates a downstream repeater has reported a Hot Plug event, indicating addition of a new receiver. This bit will be cleared on read.
3 R RX_DETECT Receiver Detect : This bit indicates that a downstream Receiver has been detected.
2 R KSV_LIST_RDY HDCP Repeater KSV List Ready : This bit indicates that the Receiver KSV list has been read and is available in the KSV_FIFO registers. The device will wait for the controller to set the KSV_LIST_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_LIST_VALID bit.
1 R KSV_RDY HDCP Receiver KSV Ready : This bit indicates that the Receiver KSV has been read and is available in the HDCP_BKSV registers. If the de-vice is not a Repeater, it will wait for the controller to set the KSV_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_VALID bit.
0 R AUTHED HDCP Authenticated: Indicates the HDCP authentication has completed successfully. The controller may now send video data requiring content protection. This bit will be cleared if authentication is lost or if the controller restarts authentication.
198 0xC6 ICR 7 RW 0x00 IE_IND_ACC Interrupt on Indirect Access Complete: Enables interrupt on completion of Indirect Register Access.
6 RW IE_RXDET_INT Interrupt on Receiver Detect: Enables interrupt on detection of a downstream Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect.
5 RW IE_RX_INT Interrupt on Receiver interrupt: Enables interrupt on indication from the HDCP Receiver. Allows propagation of interrupts from downstream devices.
4 RW IE_LIST_RDY Interrupt on KSV List Ready: Enables interrupt on KSV List Ready.
3 RW IE_KSV_RDY Interrupt on KSV Ready: Enables interrupt on KSV Ready.
2 RW IE_AUTH_FAIL Interrupt on Authentication Failure: Enables interrupt on authentication failure or loss of authentication.
1 RW IE_AUTH_PASS Interrupt on Authentication Pass: Enables interrupt on successful completion of authentication.
0 RW INT_EN Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller.
199 0xC7 ISR 7 R 0x00 IS_IND_ACC Interrupt on Indirect Access Complete: Indirect Register Access has completed.
6 R IS_RXDET_INT Interrupt on Receiver Detect interrupt: A downstream receiver has been detected. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect.
5 R IS_RX_INT Interrupt on Receiver interrupt: Receiver has indicated an interrupt request from down-stream device.
4 R IS_LIST_RDY Interrupt on KSV List Ready: The KSV list is ready for reading by the controller.
3 R IS_KSV_RDY Interrupt on KSV Ready: The Receiver KSV is ready for reading by the controller.
2 R IS_AUTH_FAIL Interrupt on Authentication Failure: Authentication failure or loss of authentication has occurred.
1 R IS_AUTH_PASS Interrupt on Authentication Pass: Authentication has completed successfully.
0 R INT Global Interrupt: Set if any enabled interrupt is indicated.
200 0xC8 NVM_CTL 7 R 0x00 NVM_PASS NVM Verify pass: This bit indicates the completion status of the NVM verification process. This bit is valid only when NVM_DONE is asserted.
0: NVM Verify failed.
1: NVM Verify passed.
6 R NVM_DONE NVM Verify done: This bit indicates that the NVM Verification has completed.
5 RW NVM_PARALLEL NVM Parallel Load Enable: Setting this bit enables external parallel data to be written to NVM SRAM. Byte data and a memory clock are brought in on the R[7:0] and G[0] pins respectively. In this mode of operation NVM_DATA[0] acts as a memory enable to enable writes to the NVM SRAM.
4:3 Reserved.
2 RW 0x00 NVM_VFY NVM Verify: Setting this bit will enable a verification of the NVM contents. This is done by reading all NVM keys, computing a SHA-1 hash value, and verifying against the SHA-1 hash stored in NVM. This bit will be cleared upon completion of the NVM Verification.
1 RW NVM_PROG NVM Program: Setting this bit to a 1 allows programming of the NVM memory from the NVM SRAM.
0 RW NVM_PROG_EN NVM Program Enable: Set to a 1 to allow erase or programming of NVM.
206 0xCE BLUE_SCREEN 7:0 RW 0xFF BLUE_SCREEN_VAL Blue Screen Data Value: Provides the 8-bit data value sent on the Blue channel when the HDCP Transmitter is sending a blue screen.
224 0xE0 HDCP_DBG_ALIAS 7:0 R HDCP_DBG Read-only alias of HDCP_DBG register.
226 0xE2 HDCP_CFG_ALIAS 7:0 R HDCP_CFG Read-only alias of HDCP_CFG register.
227 0xE3 HDCP_CTL_ALIAS 7:0 R HDCP_CTL Read-only alias of HDCP_CTL register.
228 0xE4 HDCP_STS_ALIAS 7:0 R HDCP_STS Read-only alias of HDCP_STS register.
230 0xE6 HDCP_ICR_ALIAS 7:0 R HDCP_ICR Read-only alias of HDCP_ICR register.
231 0xE7 HDCP_ISR_ALIAS 7:0 R HDCP_ISR Read-only alias of HDCP_ISR register.
240 0xF0 TX ID 7:0 R 0x5F ID0 First byte ID code: "_".
241 0xF1 7:0 R 0x55 ID1 Second byte of ID code: "U".
242 0xF2 7:0 R 0x48 ID2 Third byte of ID code: "H".
243 0xF3 7:0 R 0x39 ID3 Fourth byte of ID code: "9".
244 0xF4 7:0 R 0x34 ID4 Fifth byte of ID code: "4".
245 0xF5 7:0 R 0x39 ID5 Sixth byte of ID code: “9”.

NOTE

Registers 0x40, 0x41, and 0x42 of the Serial Control Bus Registers are used to access the Page 0x10 and 0x14 registers.

Table 11. Page 0x10 Register

ADD
(dec)		 ADD
(hex)		 REGISTER NAME BIT(S) REGISTER
TYPE		 DEFAULT
(hex)		 FUNCTION DESCRIPTION
73 0x49 OLDI_PLL_STATE_MC_CNTL 7:5 0x00 Reserved
4 RW OLDI_STATE_MC_RESET Enable HDMI PLL reset state
0: Disable state machine reset (normal operation).
1: Enable state machine reset.
3:0 Reserved, when writing to this register always write '0000b to these bits.

Table 12. Page 0x14 Register

ADD
(dec)		 ADD
(hex)		 REGISTER NAME BIT(S) REGISTER
TYPE		 DEFAULT
(hex)		 FUNCTION DESCRIPTION
73 0x49 FPD_PLL_STATE_MC_CNTL 7:5 0x00 Reserved
4 RW FPD_STATE_MC_RESET Enable FPD PLL reset state
0: Disable state machine reset (normal operation).
1: Enable state machine reset.
3:0 Reserved, when writing to this register always write '0000b to these bits.
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