ZHCSIO8
August 2018
DS90UH949A-Q1
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
应用 图
4
修订历史记录
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
DC and AC Serial Control Bus Characteristics
6.8
Recommended Timing for the Serial Control Bus
6.9
Timing Diagrams
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
High-Definition Multimedia Interface (HDMI)
7.3.1.1
HDMI Receive Controller
7.3.2
Transition Minimized Differential Signaling
7.3.3
Enhanced Display Data Channel
7.3.4
Extended Display Identification Data (EDID)
7.3.4.1
External Local EDID (EEPROM)
7.3.4.2
Internal EDID (SRAM)
7.3.4.3
External Remote EDID
7.3.4.4
Internal Pre-Programmed EDID
7.3.5
Consumer Electronics Control (CEC)
7.3.6
+5-V Power Signal
7.3.7
Hot Plug Detect (HPD)
7.3.8
High-Speed Forward Channel Data Transfer
7.3.9
Back Channel Data Transfer
7.3.10
FPD-Link III Port Register Access
7.3.11
Power Down (PDB)
7.3.12
Serial Link Fault Detect
7.3.13
Interrupt Pin (INTB)
7.3.14
Remote Interrupt Pin (REM_INTB)
7.3.15
General-Purpose I/O
7.3.15.1
GPIO[3:0] and D_GPIO[3:0] Configuration
7.3.15.2
Back Channel Configuration
7.3.15.3
GPIO_REG[8:5] Configuration
7.3.16
SPI Communication
7.3.16.1
SPI Mode Configuration
7.3.16.2
Forward Channel SPI Operation
7.3.16.3
Reverse Channel SPI Operation
7.3.17
Backward Compatibility
7.3.18
Audio Modes
7.3.18.1
HDMI Audio
7.3.18.2
DVI I2S Audio Interface
7.3.18.2.1
I2S Transport Modes
7.3.18.2.2
I2S Repeater
7.3.18.3
AUX Audio Channel
7.3.18.4
TDM Audio Interface
7.3.19
HDCP
7.3.19.1
HDCP I2S Audio Encryption
7.3.20
Built-In Self Test (BIST)
7.3.20.1
BIST Configuration and Status
7.3.20.2
Forward Channel and Back Channel Error Checking
7.3.21
Internal Pattern Generation
7.3.21.1
Pattern Options
7.3.21.2
Color Modes
7.3.21.3
Video Timing Modes
7.3.21.4
External Timing
7.3.21.5
Pattern Inversion
7.3.21.6
Auto Scrolling
7.3.21.7
Additional Features
7.3.22
Spread Spectrum Clock Tolerance
7.4
Device Functional Modes
7.4.1
Mode Select Configuration Settings (MODE_SEL[1:0])
7.4.2
FPD-Link III Modes of Operation
7.4.2.1
Single Link Operation
7.4.2.2
Dual Link Operation
7.4.2.3
Replicate Mode
7.4.2.4
Auto-Detection of FPD-Link III Modes
7.4.2.5
Frequency detection circuit may reset the FPD-Link III PLL during a temperature ramp
7.5
Programming
7.5.1
Serial Control Bus
7.5.2
Multi-Master Arbitration Support
7.5.3
I2C Restrictions on Multi-Master Operation
7.5.4
Multi-Master Access to Device Registers for Newer FPD-Link III Devices
7.5.5
Multi-Master Access to Device Registers for Older FPD-Link III Devices
7.5.6
Restrictions on Control Channel Direction for Multi-Master Operation
7.5.7
Prevention of I2C Faults During Abrupt System Faults
7.6
Register Maps
8
Application and Implementation
8.1
Applications Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
High-Speed Interconnect Guidelines
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
器件和文档支持
11.1
文档支持
11.1.1
相关文档
11.2
接收文档更新通知
11.3
社区资源
11.4
商标
11.5
静电放电警告
11.6
术语表
12
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RGC|64
MPQF125F
散热焊盘机械数据 (封装 | 引脚)
RGC|64
QFND476B
订购信息
zhcsio8_oa
7.3.15
General-Purpose I/O
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