7.3.1 Parallel LVDS Data Transfer (Color Bit Mapping Select)

The DS92LV042x can be configured to accept or transmit 24-bit data with two different LVDS parallel interface mapping schemes:

• The normal Channel Link LVDS format (MSBs on LVDS Channel 3) can be selected by configuring the MAPSEL pin to high. See Figure 23 for the normal Channel Link LVDS mapping.
• An alternate mapping scheme is available (LSBs on LVDS Channel 3) by configuring the MAPSEL pin to low. See Figure 24 for the alternate LVDS mapping.

The mapping schemes can also be selected by register control. The alternate mapping scheme is useful in some applications where the receiving system, typically a display, requires the LSBs for the 24-bit color data to be sent on LVDS Channel 3.

Figure 23. 8–Bit Channel Link Mapping: MSB's on RXIN3

Figure 24. 8–Bit Channel Link Mapping: LSB's on RXIN3

7.3.2 Serial Data Transfer

The DS92LV042x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 25 illustrates the serial stream per clock cycle.

Figure 25. Channel Link II Serial Stream (DS92LV042x)

7.3.3 Video Control Signal Filter

The three control bits can be used to communicate any low speed signal. The most common use for these bits is in the display or machine vision applications. In a display application, these bits are typically assigned as: Bit 26 to DE, Bit 24 to HS, and Bit 25 to VS. In the machine vision standard, Camera Link, these bits are typically assigned: Bit 26 to DVAL, Bit 24 to LVAL, and Bit 25 to FVAL.

When operating the devices in Normal Mode, the video control signals (DE, HS, VS) have the following restrictions:

• Normal Mode with Control Signal Filter Enabled:
  • DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 clock cycles or longer.
• Normal Mode with Control Signal Filter Disabled:
  • DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Glitches of a control signal can cause a visual display error, and video control signals are defined as low frequency signals with limited transitions. Therefore, the video control signal filter feature allows for the chipset to validate and filter out any high frequency noise on the control signals (see Figure 26).

Figure 26. Video Control Signal Filter Waveform

7.3.4 Serializer Functional Description

The serializer converts a Channel Link LVDS clock and data bus to a single serial output data stream and also acts as a signal generator for the chipset Built-In Self Test (BIST) mode. The device can be configured through external pins or through the optional serial control bus. The serializer features enhanced signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis for signal conditioning, and Channel Link II data coding that provides randomization, scrambling, and DC-balancing of the data. The serializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the serial data and system spread spectrum clock support. The serializer includes power-saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V or 3.3 V) I/O compatibility (see also Optional Serial Bus Control and Built-In Self Test (BIST)).

7.3.4.1 Signal Quality Enhancers

7.3.4.1.1 Serializer VOD Select (VODSEL)

The serializer differential output voltage may be increased by setting the VODSEL pin high. When VODSEL is low, the DC VOD is at the standard (default) level. When VODSEL is high, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and extra long cable length applications. When using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal attenuation, especially with the larger de-emphasis settings. This feature may be controlled by external pin or by register.

Table 1. Serializer Differential Output Voltage

INPUT	EFFECT
VODSEL	VOD (mV)	VOD (mVp-p)
L	±300	600
H	±450	900

7.3.4.1.2 Serializer De-Emphasis (DE-EMPH)

The de-emphasis pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin must be left open if used for standard switching currents (no de-emphasis) or if used under register control. De-emphasis is selected by connecting a resistor on this pin to ground, with the R value between 0.5 kΩ and 1 MΩ, or by register setting. When using de-emphasis, TI recommends setting VODSEL = H.

Table 2. De-Emphasis Resistor Value

RESISTOR VALUE (kΩ)	DE-EMPHASIS SETTING
Open	Disabled
0.6	–12 dB
1	–9 dB
2	–6 dB
5	–3 dB

Figure 27. De-Emphasis vs R Value

7.3.5 Deserializer Functional Description

The deserializer converts a single input serial data stream to a Channel Link LVDS clock and data bus and also provides a signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through external and strap pins or through the optional serial control bus. The deserializer features enhanced signal quality on the link by supporting an integrated equalizer on the serial input and Channel Link II data encoding which provides randomization, scrambling, and DC-balancing of the data. The deserializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data, Channel Link LVDS output interface, and output spread spectrum clock generation (SSCG) support. The deserializer includes power saving features with a power-down mode and optional LVCMOS (1.8-V) interface compatibility.

7.3.5.2 EMI Reduction Features

7.3.5.2.1 Deserializer VOD Select (VODSEL)

The differential output voltage of the Channel Link parallel interface is controlled by the VODSEL input.

Table 4. Deserializer Differential Output Voltage

INPUT	EFFECT
VODSEL	VOD (mV)	VOD (mVp-p)
L	±250	500
H	±400	800

7.3.5.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)

The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.

7.3.5.2.3 Deserializer SSCG Generation (Optional)

The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total) at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external pins or by register.

NOTE

The deserializer supports the SSCG function with TXCLKOUT = 10 MHz to 65 MHz. When the TXCLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function (SSC[2:0] = 000).

Figure 28. SSCG Waveform

Table 5. SSCG Configuration (LFMODE = L): Deserializer Output

SSC[2:0] INPUTS LFMODE = L (20 TO 65 MHz)			RESULT
SSC2	SSC1	SSC0	fdev (%)	fmod (kHz)
L	L	L	Off	Off
L	L	H	±0.9	CLK/2168
L	H	L	±1.2
L	H	H	±1.9
H	L	L	±2.3
H	L	H	±0.7	CLK/1300
H	H	L	±1.3
H	H	H	±1.7

Table 6. SSCG Configuration (LFMODE = H): Deserializer Output

SSC[2:0] INPUTS LFMODE = H (10 TO 20 MHz)			RESULT
SSC2	SSC1	SSC0	fdev (%)	fmod (kHz)
L	L	L	Off	Off
L	L	H	±0.7	CLK/625
L	H	L	±1.3
L	H	H	±1.8
H	L	L	±2.2
H	L	H	±0.7	CLK/385
H	H	L	±1.2
H	H	H	±1.7

7.3.5.2.4 Power-Saving Features

7.3.5.2.4.1 Deserializer Power-Down Feature (PDB)

The deserializer has a PDB input pin to enable or power down the device. This pin can be controlled by the system to save power, disabling the deserializer when the display is not required. An auto-detect mode is also available. In this mode, the PDB pin is tied high and the deserializer enters power-down when the serial stream stops. When the serial stream starts up again, the deserializer locks to the input stream, asserts the LOCK pin, and outputs valid data. In power-down mode, the LVDS data and clock output states are determined by the OSS_SEL status.

NOTE

In power-down, the optional serial bus control registers are RESET.

7.3.5.2.4.2 Deserializer Stop Stream SLEEP Feature

The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer then locks to the incoming signal and recovers the data.

NOTE

In STOP STREAM SLEEP, the optional serial bus control registers values are RETAINED.

7.3.5.2.4.3 Deserializer 1.8-V or 3.3-V VDDIO Operation

The deserializer parallel control bus can operate with 1.8-V or 3.3-V levels (V_DDIO) for target (display) compatibility. The 1.8-V levels offers lower noise (EMI) and also system power savings.

7.3.5.4 Deserializer Oscillator Output (Optional)

The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by external pin or by register.

Figure 29. TXCLKOUT Output Oscillator Option Enabled

7.3.6 Built-In Self Test (BIST)

An optional at-speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode, only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power-down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin.

Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3); see respective data sheets for details on entering BIST mode and control.

7.3.6.1 Sample BIST Sequence

See Figure 30 for the BIST mode flow diagram.

Step 1: Place the serializer in BIST Mode by setting serializer BISTEN = H. BIST Mode is enabled through the BISTEN pin. An RXCLKIN is required for BIST. When the deserializer detects the BIST mode pattern and command (DCA and DCB code), the data and control signal outputs are shut off.

Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The deserializer is now in BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there is one or more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The link returns to normal operation.

Figure 31 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx equalization).

Figure 30. BIST Mode Flow Diagram

Figure 31. BIST Waveforms

7.3.7 Optional Serial Bus Control

The serializer and deserializer may also be configured by the use of a serial control bus that is I²C protocol-compatible. By default, the I²C Reg 0x00 = 0x00, and all configuration is set by control or strap pins. Writing Reg 0x00 = 0x01 enables or allows configuration by registers; this overrides the control or strap pins. Multiple devices may share the serial control bus, because multiple addresses are supported (see Figure 32).

The serial bus is comprised of three pins. The SCL is a serial bus clock input. The SDA is the serial bus data input or output signal. Both SCL and SDA signals require an external pullup resistor to V_DDIO. For most applications, a 4.7-kΩ pullup resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low.

Figure 32. Serial Control Bus Connection

The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are possible:

• The pin may be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor.
• The pin may be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor and pulled down to ground with a recommended value RID resistor. This creates a voltage divider that sets the other three possible addresses.

See Table 8 for the serializer and Table 9 for the deserializer. Do not tie ID[X] directly to VSS.

The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when SCL transitions low while SDA is high. A STOP occurs when SDA transitions high while SCL is also high (see Figure 33).

Figure 33. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 34 and a WRITE is shown in Figure 35.

If the serial bus is not required, the three pins may be left open (NC).

Figure 34. Serial Control Bus: READ

Figure 35. Serial Control Bus: WRITE

7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])

The DS92LV042x chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices. Configuration modes are provided for reverse compatibility with the DS90C241 or DS90C124 chipset (FPD-Link II Generation 1) and also the DS90UR241 / DS90UR124 chipset (FPD-Link II Generation 2) by setting the respective mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 10 and Table 11. This selection also determines whether the control signal filter feature is enabled or disabled in the normal mode. This feature may be controlled by external pin or by register.

Table 12. SERIALIZER: Serial Bus Control Registers

Table 13. DESERIALIZER: Serial Bus Control Registers