ZHCSBK0D October 2012 – October 2015 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2
PRODUCTION DATA.
Figure 4-1 illustrates the ball locations for the 289-ball ZWT new fine pitch ball grid array package and is used in conjunction with Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5 to locate signal names and ball grid numbers.
Figure 4-2 through Figure 4-5 show the terminal assignments on the 289-ball ZWT package in four quadrants (A, B, C, and D). See Table 4-1 for the complete multiplexed signal names.
Table 4-1 describes the signals.
TERMINAL | I/O/Z(2) | DESCRIPTION | PU or PD(3) |
OUTPUT BUFFER STRENGTH |
|
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NAME | ZWT BALL NO. |
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ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1 | |||||
ADC1VREFHI | A12 | I | ADC1 External High Reference – used only when in ADC external reference mode. | ||
ADC1VREFLO | see VSSA | I | ADC1 External Low Reference – used only when in ADC external reference mode. | ||
ADC1INA0 | C13 | I | ADC1 Group A, Channel 0 input | ||
ADC1INA2 | B13 | I | ADC1 Group A, Channel 2 input | 4 mA | |
COMPA1 | I | Comparator Input A1 | |||
AIO2 | I/O | Digital AIO2 | |||
ADC1INA3 | B12 | I | ADC1 Group A, Channel 3 input | ||
ADC1INA4 | A11 | I | ADC1 Group A, Channel 4 input | 4 mA | |
COMPA2 | I | Comparator Input A2 | |||
AIO4 | I/O | Digital AIO4 | |||
ADC1INA6 | C12 | I | ADC1 Group A, Channel 6 input | 4 mA | |
COMPA3 | I | Comparator Input A3 | |||
AIO6 | I/O | Digital AIO6 | |||
ADC1INA7 | B11 | I | ADC1 Group A, Channel 7 input | ||
ADC1INB0 | A13 | I | ADC1 Group B, Channel 0 input | ||
ADC1INB2 | A14 | I | ADC1 Group B, Channel 2 input | 4 mA | |
COMPB1 | I | Comparator Input B1 | |||
AIO10 | I/O | Digital AIO10 | |||
ADC1INB3 | B14 | I | ADC1 Group B, Channel 3 input | ||
ADC1INB4 | C14 | I | ADC1 Group B, Channel 4 input | 4 mA | |
COMPB2 | I | Comparator Input B2 | |||
AIO12 | I/O | Digital AIO12 | |||
ADC1INB6 | B15 | I | ADC1 Group B, Channel 6 input | 4 mA | |
COMPB3 | I | Comparator Input B3 | |||
AIO14 | I/O | Digital AIO14 | |||
ADC1INB7 | C15 | I | ADC1 Group B, Channel 7 input | ||
ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2 | |||||
ADC2VREFHI | A8 | I | ADC2 External High Reference – used only when in ADC external reference mode. | ||
ADC2VREFLO | see VSSA | I | ADC2 External Low Reference – used only when in ADC external reference mode. | ||
ADC2INA0 | C8 | I | ADC2 Group A, Channel 0 input | ||
ADC2INA2 | B8 | I | ADC2 Group A, Channel 2 input | 4 mA | |
COMPA4 | I | Comparator Input A4 | |||
AIO18 | I/O | Digital AIO18 | |||
ADC2INA3 | B9 | I | ADC2 Group A, Channel 3 input | ||
ADC2INA4 | A9 | I | ADC2 Group A, Channel 4 input | 4 mA | |
COMPA5 | I | Comparator Input A5 | |||
AIO20 | I/O | Digital AIO20 | |||
ADC2INA6 | B10 | I | ADC2 Group A, Channel 6 input | 4 mA | |
COMPA6 | I | Comparator Input A6 | |||
AIO22 | I/O | Digital AIO22 | |||
ADC2INA7 | A10 | I | ADC2 Group A, Channel 7 input | ||
ADC2INB0 | A7 | I | ADC2 Group B, Channel 0 input | ||
ADC2INB2 | B7 | I | ADC2 Group B, Channel 2 input | 4 mA | |
COMPB4 | I | Comparator Input B4 | |||
AIO26 | I/O | Digital AIO26 | |||
ADC2INB3 | A6 | I | ADC2 Group B, Channel 3 input | ||
ADC2INB4 | B6 | I | ADC2 Group B, Channel 4 input | 4 mA | |
COMPB5 | I | Comparator Input B5 | |||
AIO28 | I/O | Digital AIO28 | |||
ADC2INB6 | A5 | I | ADC2 Group B, Channel 6 input | 4 mA | |
COMPB6 | I | Comparator Input B6 | |||
AIO30 | I/O | Digital AIO30 | |||
ADC2INB7 | B5 | I | ADC2 Group B, Channel 7 input | ||
ADC Modules Analog Power and Ground | |||||
VDDA | C9 | 3.3-V Analog Module Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. |
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VDDA | C10 | 3.3-V Analog Module Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. |
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VDDA | C11 | 3.3-V Analog Module Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. |
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VSSA | D8 | Analog ground for ADC1, ADC2, ADC1VREFLO, ADC2VREFLO, COMP1–6, and DAC1–3 | |||
VSSA | D9 | Analog ground for ADC1, ADC2, ADC1VREFLO, ADC2VREFLO, COMP1–6, and DAC1–3 | |||
VSSA | D10 | Analog ground for ADC1, ADC2, ADC1VREFLO, ADC2VREFLO, COMP1–6, and DAC1–3 | |||
VSSA | D11 | Analog ground for ADC1, ADC2, ADC1VREFLO, ADC2VREFLO, COMP1–6, and DAC1–3 | |||
Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only) | |||||
GPIO192 | A4 | I/O | General-purpose input/output 192 | PU | 4 mA |
GPIO193 | B4 | I/O | General-purpose input/output 193 | PU | 4 mA |
COMP1OUT | O | Compare result from Analog Comparator 1 | |||
GPIO194 | B3 | I/O | General-purpose input/output 194 | PU | 4 mA |
COMP6OUT | O | Compare result from Analog Comparator 6 | |||
GPIO195 | B2 | I/O | General-purpose input/output 195 | PU | 4 mA |
COMP2OUT | O | Compare result from Analog Comparator 2 | |||
GPIO196 | A16 | I/O | General-purpose input/output 196 | PU | 8 mA |
COMP3OUT | O | Compare result from Analog Comparator 3 | |||
GPIO197 | B16 | I/O | General-purpose input/output 197 | PU | 4 mA |
COMP4OUT | O | Compare result from Analog Comparator 4 | |||
GPIO198 | A17 | I/O | General-purpose input/output 198 | PU | 4 mA |
GPIO199(4) | B17 | I/O | General-purpose input/output 199 | PU | 8 mA |
COMP5OUT | O | Compare result from Analog Comparator 5 | |||
GPIO Group 1 and Peripheral Signals | |||||
PA0_GPIO0 | D1 | I/O/Z | General-purpose input/output 0 | PU | 4 mA |
M_U0RX | I | UART-0 receive data | |||
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
M_U1RX | I | UART-1 receive data | |||
C_EPWM1A | O | Enhanced PWM-1 output A | |||
PA1_GPIO1 | E3 | I/O/Z | General-purpose input/output 1 | PU | 4 mA |
M_U0TX | O | UART-0 transmit data | |||
M_I2C1SDA | I/OD | I2C-1 data open-drain bidirectional port | |||
M_U1TX | O | UART-1 data transmit | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
C_EPWM1B | O | Enhanced PWM-1 output B | |||
C_ECAP6 | I/O | Enhanced Capture-6 input/output | |||
PA2_GPIO2 | E2 | I/O/Z | General-purpose input/output 2 | PU | 4 mA |
M_SSI0CLK | I/O | SSI-0 clock | |||
M_MIITXD2 | O | EMAC MII transmit data bit 2 | |||
C_EPWM2A | O | Enhanced PWM-2 output A | |||
PA3_GPIO3 | E1 | I/O/Z | General-purpose input/output 3 | PU | 4 mA |
M_SSI0FSS | I/O | SSI-0 frame | |||
M_MIITXD1 | O | EMAC MII transmit data bit 1 | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
C_EPWM2B | O | Enhanced PWM-2 output B | |||
C_ECAP5 | I/O | Enhanced Capture-5 input/output | |||
PA4_GPIO4 | F4 | I/O/Z | General-purpose input/output 4 | PU | 4 mA |
M_SSI0RX | I | SSI-0 receive data | |||
M_MIITXD0 | O | EMAC MII transmit data bit 0 | |||
M_CAN0RX | I | CAN-0 receive data | |||
C_EPWM3A | O | Enhanced PWM-3 output A | |||
PA5_GPIO5 | F3 | I/O/Z | General-purpose input/output 5 | PU | 4 mA |
M_SSI0TX | O | SSI-0 transmit data | |||
M_MIIRXDV | I | EMAC MII receive data valid | |||
M_CAN0TX | O | CAN-0 transmit data | |||
C_EPWM3B | O | Enhanced PWM-3 output B | |||
C_MFSRA | I | McBSP-A receive frame sync | |||
C_ECAP1 | I/O | Enhanced Capture-1 input/output | |||
PA6_GPIO6 | F2 | I/O/Z | General-purpose input/output 6 | PU | 4 mA |
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
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M_MIIRXCK | I | EMAC MII receive clock | |||
M_CAN0RX | I | CAN-0 receive data | |||
M_USB0EPEN | O | USB-0 external power enable (optionally used in host mode) |
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C_EPWM4A | O | Enhanced PWM-4 output A | |||
C_EPWMSYNCO | O | Enhanced PWM-4 external sync pulse | |||
PA7_GPIO7 | F1 | I/O/Z | General-purpose input/output 7 | PU | 4 mA |
M_I2C1SDA | I/OD | I2C-1 data open-drain bidirectional port | |||
M_CCP4 | I/O | Capture/Compare/PWM-4 (General-purpose Timer) |
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M_MIIRXER | I | EMAC MII receive error | |||
M_CAN0TX | O | CAN-0 transmit data | |||
M_CCP3 | I/O | Capture/Compare/PWM-3 (General-purpose Timer) |
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M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
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M_MIIRXD1 | I | EMAC MII receive data 1 | |||
C_EPWM4B | O | Enhanced PWM-4 output B | |||
C_MCLKRA | I | McBSP-A receive clock | |||
C_ECAP2 | I/O | Enhanced Capture-1 input/output | |||
PB0_GPIO8 | G4 | I/O/Z | General-purpose input/output 8 | PU | 4 mA |
M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
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M_U1RX | I | UART-1 data receive data | |||
M_SSI2TX | O | SSI-2 transmit data | |||
M_CAN1TX | O | CAN-1 transmit data | |||
M_U4TX | O | UART-4 transmit data | |||
C_EPWM5A | O | Enhanced PWM-5 output A | |||
C_ADCSOCAO | O | ADC start-of-conversion A | |||
PB1_GPIO9 | G3 | I/O/Z | General-purpose input/output 9 | PU | 4 mA |
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
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M_U1TX | O | UART-1 transmit data | |||
M_SSI2RX | I | SSI-2 receive data | |||
C_EPWM5B | O | Enhanced PWM-5 output B | |||
C_ECAP3 | I/O | Enhanced Capture-3 input/output | |||
PB2_GPIO10 | G2 | I/O/Z | General-purpose input/output 10 | PU | 4 mA |
M_I2C0SCL | I/OD | I2C-0 clock open-drain bidirectional port | |||
M_CCP3 | I/O | Capture/Compare/PWM-3 (General-purpose Timer) |
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M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
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M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
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M_SSI2CLK | I/O | SSI-2 clock | |||
M_CAN1RX | I | CAN-1 receive data | |||
M_U4RX | I | UART-4 receive data | |||
C_EPWM6A | O | Enhanced PWM-6 output A | |||
C_ADCSOCBO | O | ADC start-of-conversion B | |||
PB3_GPIO11 | G1 | I/O/Z | General-purpose input/output 11 | PU | 4 mA |
M_I2C0SDA | I/OD | I2C-0 data open-drain bidirectional port | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
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M_SSI2FSS | I/O | SSI-2 frame | |||
M_U1RX | I | UART-1 receive data | |||
C_EPWM6B | O | Enhanced PWM-6 output B | |||
C_ECAP4 | I/O | Enhanced Capture-4 input/output | |||
PB4_GPIO12 | N4 | I/O/Z | General-purpose input/output 12 | PU | 4 mA |
M_U2RX | I | UART-2 receive data | |||
M_CAN0RX | I | CAN-0 receive data | |||
M_U1RX | I | UART-1 receive data | |||
M_EPI0S23 | I/O | EPI-0 signal 23 | |||
M_CAN1TX | O | CAN-1 transmit data | |||
M_SSI1TX | O | SSI-1 transmit data | |||
C_EPWM7A | O | Enhanced PWM-7 output A | |||
PB5_GPIO13 | M4 | I/O/Z | General-purpose input/output 13 | PU | 4 mA |
M_CCP5 | I/O | Capture/Compare/PWM-5 (General-purpose Timer) |
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M_CCP6 | I/O | Capture/Compare/PWM-6 (General-purpose Timer) |
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M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
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M_CAN0TX | O | CAN-0 transmit data | |||
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_U1TX | O | UART-1 transmit data | |||
M_EPI0S22 | I/O | EPI-0 signal 22 | |||
M_CAN1RX | I | CAN-1 receive data | |||
M_SSI1RX | I | SSI-1 receive data | |||
C_EPWM7B | O | Enhanced PWM-7 output B | |||
PB6_GPIO14 | H4 | I/O/Z | General-purpose input/output 14 | PU | 4 mA |
M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
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M_CCP7 | I/O | Capture/Compare/PWM-7 (General-purpose Timer) |
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M_CCP5 | I/O | Capture/Compare/PWM-5 (General-purpose Timer) |
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M_EPI0S37(5) | I/O | EPI-0 signal 37 | |||
M_MIICRS | I | EMAC MII carrier sense | |||
M_I2C0SDA | I/OD | I2C-0 data open-drain bidirectional port | |||
M_U1TX | O | UART-1 transmit data | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
C_EPWM8A | O | Enhanced PWM-8 output A | |||
PB7_GPIO15 | H3 | I/O/Z | General-purpose input/output 15 | PU | 4 mA |
M_EXTNMI | I | Cortex-M3 external nonmaskable interrupt | |||
M_MIIRXD1 | I | EMAC MII receive data 1 | |||
M_EPI0S36(5) | I/O | EPI-0 signal 36 | |||
M_I2C0SCL | I/OD | I2C-0 clock open-drain bidirectional port | |||
M_U1RX | I | UART-1 receive data | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
C_EPWM8B | O | Enhanced PWM-8 output B | |||
PD0_GPIO16 | F16 | I/O/Z | General-purpose input/output 16 | PU | 4 mA |
M_CAN0RX | I | CAN-0 receive data | |||
M_U2RX | I | UART-2 receive data | |||
M_U1RX | I | UART-1 receive data | |||
M_CCP6 | I/O | Capture/Compare/PWM-6 (General-purpose Timer) |
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M_MIIRXDV | I | EMAC MII receive data valid | |||
M_MIIRXD2 | I | EMAC MII receive data 2 | |||
M_SSI0TX | O | SSI-0 transmit data | |||
M_CAN1TX | O | CAN-1 transmit data | |||
M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
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C_SPISIMOA | I/O | SPI-A slave in, master out | |||
PD1_GPIO17 | F19 | I/O/Z | General-purpose input/output 17 | PU | 4 mA |
M_CAN0TX | O | CAN-0 transmit data | |||
M_U2TX | O | UART-2 transmit data | |||
M_U1TX | O | UART-1 transmit data | |||
M_CCP7 | I/O | Capture/Compare/PWM-7 (General-purpose Timer) |
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M_MIITXER | O | EMAC MII transmit error | |||
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_MIICOL | I | EMAC MII collision detect | |||
M_SSI0RX | I | SSI-0 receive data | |||
M_CAN1RX | I | CAN-1 receive data | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
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C_SPISOMIA | I/O | SPI-A master in, slave out | |||
PD2_GPIO18 | W5 | I/O/Z | General-purpose input/output 18 | PU | 4 mA |
M_U1RX | I | UART-1 receive data | |||
M_CCP6 | I/O | Capture/Compare/PWM-6 (General-purpose Timer) |
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M_CCP5 | I/O | Capture/Compare/PWM-5 (General-purpose Timer) |
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M_EPI0S20 | I/O | EPI-0 signal 20 | |||
M_SSI0CLK | I/O | SSI-0 clock | |||
M_U1TX | O | UART-1 transmit data | |||
M_CAN0RX | I | CAN-0 receive data | |||
C_SPICLKA | I/O | SPI-A clock | |||
PD3_GPIO19 | W6 | I/O/Z | General-purpose input/output 19 | PU | 4 mA |
M_U1TX | O | UART-1 transmit data | |||
M_CCP7 | I/O | Capture/Compare/PWM-7 (General-purpose Timer) |
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M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
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M_EPI0S21 | I/O | EPI-0 signal 21 | |||
M_SSI0FSS | I/O | SSI-0 frame | |||
M_U1RX | I | UART-1 receive data | |||
M_CAN0TX | O | CAN-0 transmit data | |||
C_SPISTEA | I/O | SPI-A slave transmit enable | |||
PD4_GPIO20 | U16 | I/O/Z | General-purpose input/output 20 | PU | 4 mA |
M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
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M_CCP3 | I/O | Capture/Compare/PWM-3 (General-purpose Timer) |
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M_MIITXD3 | O | EMAC MII transmit data 3 | |||
M_EPI0S19 | I/O | EPI-0 signal 19 | |||
M_U3TX | O | UART-3 transmit data | |||
M_CAN1TX | O | CAN-1 transmit data | |||
C_EQEP1A | I | Enhanced QEP-1 input A | |||
C_MDXA | O | McBSP-A transmit data | |||
PD5_GPIO21 | U17 | I/O/Z | General-purpose input/output 21 | PU | 6 mA |
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_CCP4 | I/O | Capture/Compare/PWM-4 (General-purpose Timer) |
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M_MIITXD2 | O | EMAC MII transmit data 2 | |||
M_U2RX | I | UART-2 receive data | |||
M_EPI0S28 | I/O | EPI-0 signal 28 | |||
M_U3RX | I | UART-3 receive data | |||
M_CAN1RX | I | CAN-1 receive data | |||
C_EQEP1B | I | Enhanced QEP-1 input B | |||
C_MDRA | I | McBSP-A receive data | |||
PD6_GPIO22 | V17 | I/O/Z | General-purpose input/output 22 | PU | 6 mA |
M_MIITXD1 | O | EMAC MII transmit data 1 | |||
M_U2TX | O | UART-2 transmit data | |||
M_EPI0S29 | I/O | EPI-0 signal 29 | |||
M_I2C1SDA | I/OD | I2C-0 data open-drain bidirectional port | |||
M_U1TX | O | UART-1 transmit data | |||
C_EQEP1S | I/O | Enhanced QEP-1 strobe | |||
C_MCLKXA | O | McBSP-A transmit clock | |||
PD7_GPIO23 | W17 | I/O/Z | General-purpose input/output 23 | PU | 6 mA |
M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
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M_MIITXD0 | O | EMAC MII transmit data 0 | |||
M_EPI0S30 | I/O | EPI-0 signal 30 | |||
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
M_U1RX | I | UART-1 receive data | |||
C_EQEP1I | I/O | Enhanced QEP-1 index | |||
C_MFSXA | O | McBSP-A transmit frame sync | |||
PE0_GPIO24 | W10 | I/O/Z | General-purpose input/output 24 | PU | 4 mA |
M_SSI1CLK | I/O | SSI-1 clock | |||
M_CCP3 | I/O | Capture/Compare/PWM-3 (General-purpose Timer) |
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M_EPI0S8 | I/O | EPI-0 signal 8 | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
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M_SSI3TX | O | SSI-3 transmit data | |||
M_CAN0RX | I | CAN-1 receive data | |||
M_SSI1TX | O | SSI-1 transmit data | |||
C_ECAP1 | I/O | Enhanced Capture-1 input/output | |||
C_EQEP2A | I | Enhanced QEP-2 input A | |||
PE1_GPIO25 | W9 | I/O/Z | General-purpose input/output 25 | PU | 4 mA |
M_SSI1FSS | I/O | SSI-1 frame | |||
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_CCP6 | I/O | Capture/Compare/PWM-6 (General-purpose Timer) |
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M_EPI0S9 | I/O | EPI-0 signal 9 | |||
M_SSI3RX | I | SSI-3 receive data | |||
M_CAN0TX | O | CAN-1 transmit data | |||
M_SSI1RX | O | SSI-1 receive data | |||
C_ECAP2 | I/O | Enhanced Capture-2 input/output | |||
C_EQEP2B | I | Enhanced QEP-2 input B | |||
PE2_GPIO26 | U6 | I/O/Z | General-purpose input/output 26 | PU | 4 mA |
M_CCP4 | I/O | Capture/Compare/PWM-4 (General-purpose Timer) |
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M_SSI1RX | I | SSI-1 receive data | |||
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_EPI0S24 | I/O | EPI-0 signal 24 | |||
M_SSI3CLK | I/O | SSI-3 clock | |||
M_U2RX | I | UART-2 receive data | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
C_ECAP3 | I/O | Enhanced Capture-3 input/output | |||
C_EQEP2I | I/O | Enhanced QEP-2 index | |||
PE3_GPIO27 | V6 | I/O/Z | General-purpose input/output 27 | PU | 4 mA |
M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
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M_SSI1TX | O | SSI-1 transmit data | |||
M_CCP7 | I/O | Capture/Compare/PWM-7 (General-purpose Timer) |
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M_EPI0S25 | I/O | EPI-0 signal 25 | |||
M_SSI3FSS | I/O | SSI-3 frame | |||
M_U2TX | O | UART-2 transmit data | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
C_ECAP4 | I/O | Enhanced Capture-4 input/output | |||
C_EQEP2S | I/O | Enhanced QEP-2 strobe | |||
PE4_GPIO28 | T18 | I/O/Z | General-purpose input/output 28 | PU | 4 mA |
M_CCP3 | I/O | Capture/Compare/PWM-3 (General-purpose Timer) |
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M_U2TX | O | UART-2 transmit data | |||
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
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M_MIIRXD0 | I | EMAC MII receive data 0 | |||
M_EPI0S34(5) | I/O | EPI-0 signal 34 | |||
M_U0RX | I | UART-0 receive data | |||
M_EPI0S38(5) | I/O | EPI-0 signal 38 | |||
M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
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C_SCIRXDA | I | SCI-A receive data | |||
PE5_GPIO29 | U19 | I/O/Z | General-purpose input/output 29 | PU | 4 mA |
M_CCP5 | I/O | Capture/Compare/PWM-5 (General-purpose Timer) |
|||
M_EPI0S35(5) | I/O | EPI-0 signal 35 | |||
M_MIITXER | O | EMAC MII transmit error | |||
M_U0TX | O | UART-0 transmit data | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
|||
C_SCITXDA | O | SCI-A transmit data | |||
PE6_GPIO30 | H2 | I/O/Z | General-purpose input/output 30 | PU | 4 mA |
M_MIIMDIO | I/O | EMAC management data input/output | |||
M_CAN0RX | I | CAN-0 receive data | |||
C_EPWM9A | O | Enhanced PWM-9 output A | |||
PE7_GPIO31 | H1 | I/O/Z | General-purpose input/output 31 | PU | 4 mA |
M_MIIRXD3 | I | EMAC MII receive data 3 | |||
M_CAN0TX | O | CAN-0 transmit data | |||
C_EPWM9B | O | Enhanced PWM-9 output B | |||
PF0_GPIO32 | D19 | I/O/Z | General-purpose input/output 32 | PU | 4 mA |
M_CAN1RX | I | CAN-1 receive data | |||
M_MIIRXCK | I | EMAC MII receive clock | |||
M_I2C0SDA | I/OD | I2C-0 data open-drain bidirectional port | |||
M_TRACED2 | O | Trace data 2 | |||
C_I2CASDA | I/OD | I2C-A data open-drain bidirectional port | |||
C_SCIRXDA | I | SCI-A receive data | |||
C_ADCSOCAO | O | ADC start-of-conversion A(6) | |||
PF1_GPIO33 | E17 | I/O/Z | General-purpose input/output 33 | PU | 4 mA |
M_CAN1TX | O | CAN-1 transmit data | |||
M_MIIRXER | I | EMAC MII receive error | |||
M_CCP3 | I/O | Capture/Compare/PWM-3 (General-purpose Timer) |
|||
M_I2C0SCL | I/OD | I2C-0 clock open-drain bidirectional port | |||
M_TRACED3 | O | Trace data 3 | |||
C_I2CASCL | I/OD | I2C-A clock open-drain bidirectional port | |||
C_EPWMSYNCO | O | Enhanced PWM sync out | |||
C_ADCSOCBO | O | ADC start-of-conversion B(6) | |||
PF2_GPIO34 | P16 | I/O/Z | General-purpose input/output 34 | PU | 4 mA |
M_MIIPHYINTR | I | EMAC PHY MII interrupt | |||
M_EPI0S32(5) | I/O | EPI-0 signal 32 | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
M_TRACECLK | O | Trace clock | |||
M_XCLKOUT | O | External output clock | |||
C_ECAP1 | I/O | Enhanced Capture-1 input/output | |||
C_SCIRXDA | I | SCI-A receive data | |||
C_XCLKOUT | O | External output clock | |||
BOOT_3 | I | Boot pin 3 | |||
PF3_GPIO35 | P17 | I/O/Z | General-purpose input/output 35 | PU | 4 mA |
M_MIIMDC | I | EMAC management data clock | |||
M_EPI0S33(5) | I/O | EPI-0 signal 33 | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
M_U0TX | O | UART-0 transmit data | |||
M_TRACED0 | O | Trace data 0 | |||
C_SCITXDA | O | SCI-A transmit data | |||
BOOT_2 | I | Boot pin 2 | |||
PF4_GPIO36 | U14 | I/O/Z | General-purpose input/output 36 | PU | 4 mA |
M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
|||
M_MIIMDIO | I/O | EMAC management data input/output | |||
M_EPI0S12 | I/O | EPI-0 signal 12 | |||
M_SSI1RX | I | SSI-1 receive data | |||
M_U0RX | I | UART-0 receive data | |||
C_SCIRXDA | I | SCI-A receive data | |||
PF5_GPIO37 | U11 | I/O/Z | General-purpose input/output 37 | PU | 4 mA |
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
|||
M_MIIRXD3 | I | EMAC MII receive data 3 | |||
M_EPI0S15 | I/O | EPI-0 signal 15 | |||
M_SSI1TX | O | SSI-1 transmit data | |||
M_MIITXEN | O | EMAC MII transmit enable | |||
C_ECAP2 | I/O | Enhanced Capture-2 input/output | |||
PF6_GPIO38 | W12 | I/O/Z | General-purpose input/output 38. If configured as an output, place a capacitor with a value of 56 pF or greater near the pin. If configured as an input, place a series resistor with a value equal to 1 kΩ or greater near the pin. See the F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2, F28M36H33C2, F28M36H33B2 Concerto MCUs Silicon Errata (SPRZ375) for details. NOTE: For this pin, only the USB0VBUS function is available on silicon revision 0 devices (GPIO and the four other functions listed are not available). |
PU | 4 mA |
M_USB0VBUS | Analog | USB0 VBUS power (5-V tolerant) | |||
M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
|||
M_MIIRXD2 | I | EMAC MII receive data 2 | |||
M_EPI0S38(5) | I/O | EPI-0 signal 38 | |||
PF7_GPIO39 | D17 | I/O/Z | General-purpose input/output 39 | PU | 4 mA |
M_CAN1TX | O | CAN-1 transmit data | |||
PG0_GPIO40 | V11 | I/O/Z | General-purpose input/output 40 | PU | 4 mA |
M_U2RX | I | UART-2 receive data | |||
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
|||
M_EPI0S13 | I/O | EPI-0 signal 13 | |||
M_MIIRXD2 | I | EMAC MII receive data 2 | |||
M_U4RX | I | UART-4 receive data | |||
M_MIITXCK | I | EMAC MII transmit clock | |||
PG1_GPIO41 | U12 | I/O/Z | General-purpose input/output 41 | PU | 4 mA |
M_U2TX | O | UART-2 transmit data | |||
M_I2C1SDA | I/OD | I2C-1 data open-drain bidirectional port | |||
M_EPI0S14 | I/O | EPI-0 signal 14 | |||
M_MIIRXD1 | I | EMAC MII receive data 1 | |||
M_U4TX | O | UART-4 transmit data | |||
M_MIITXER | O | EMAC MII transmit error | |||
PG2_GPIO42 | W14 | I/O/Z | General-purpose input/output 42 | PU | 4 mA |
M_USB0DM | Analog | USB0 data minus | |||
M_MIICOL | I | EMAC MII collision detect | |||
M_EPI0S39(5) | I/O | EPI-0 signal 39 | |||
PG3_GPIO43 | N17 | I/O/Z | General-purpose input/output 43 | PU | 4 mA |
M_MIICRS | I | EMAC MII carrier sense | |||
M_MIIRXDV | I | EMAC MII receive data valid | |||
M_TRACED1 | O | Trace data 1 | |||
BOOT_0 | I | Boot pin 0 | |||
PG4_GPIO44 | D18 | I/O/Z | General-purpose input/output 44 | PU | 4 mA |
M_CAN1RX | I | CAN-1 receive data | |||
PG5_GPIO45 | W15 | I/O/Z | General-purpose input/output 45 | PU | 4 mA |
M_USB0DP | Analog | USB0 data plus | |||
M_CCP5 | I/O | Capture/Compare/PWM-5 (General-purpose Timer) |
|||
M_MIITXEN | O | EMAC MII transmit enable | |||
M_EPI0S40(5) | I/O | EPI-0 signal 40 | |||
PG6_GPIO46 | W13 | I/O/Z | General-purpose input/output 46. If configured as an output, place a capacitor with a value of 56 pF or greater near the pin. If configured as an input, place a series resistor with a value equal to 1 kΩ or greater near the pin. See the F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2, F28M36H33C2, F28M36H33B2 Concerto MCUs Silicon Errata (SPRZ375) for details. NOTE: For this pin, only the USB0ID function is available on silicon revision 0 devices (GPIO and the three other functions listed are not available). |
PU | 4 mA |
M_USB0ID | Analog | USB0 ID (5-V tolerant) | |||
M_MIITXCK | I | EMAC MII transmit clock | |||
M_EPI0S41(5) | I/O | EPI-0 signal 41 | |||
PG7_GPIO47 | W11 | I/O/Z | General-purpose input/output 47 | PU | 6 mA |
M_MIITXER | O | EMAC MII transmit error | |||
M_CCP5 | I/O | Capture/Compare/PWM-5 (General-purpose Timer) |
|||
M_EPI0S31 | I/O | EPI-0 signal 31 | |||
M_MIICRS | I | EMAC MII carrier sense | |||
BOOT_1 | I | Boot pin 1 | |||
PH0_GPIO48 | V10 | I/O/Z | General-purpose input/output 48 | PU | 4 mA |
M_CCP6 | I/O | Capture/Compare/PWM-6 (General-purpose Timer) |
|||
M_MIIPHYRST | O | EMAC PHY MII reset | |||
M_EPI0S6 | I/O | EPI-0 signal 6 | |||
M_SSI3TX | O | SSI-3 transmit data | |||
M_MIITXD3 | O | EMAC MII transmit data 3 | |||
C_ECAP5 | I/O | Enhanced Capture-5 input/output | |||
PH1_GPIO49 | U8 | I/O/Z | General-purpose input/output 49 | PU | 4 mA |
M_CCP7 | I/O | Capture/Compare/PWM-7 (General-purpose Timer) |
|||
M_EPI0S7 | I/O | EPI-0 signal 7 | |||
M_MIIRXD0 | I | EMAC MII receive data 0 | |||
M_SSI3RX | I | SSI-3 receive data | |||
M_MIITXD2 | O | EMAC MII transmit data 2 | |||
C_ECAP6 | I/O | Enhanced Capture-6 input/output | |||
PH2_GPIO50 | V7 | I/O/Z | General-purpose input/output 50 | PU | 4 mA |
M_EPI0S1 | I/O | EPI-0 signal 1 | |||
M_MIITXD3 | O | EMAC MII transmit data 3 | |||
M_SSI3CLK | I/O | SSI-3 clock | |||
M_MIITXD1 | O | EMAC MII transmit data 1 | |||
C_EQEP1A | I | Enhanced QEP-1 input A | |||
PH3_GPIO51 | U7 | I/O/Z | General-purpose input/output 51 | PU | 4 mA |
M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
|||
M_EPI0S0 | I/O | EPI-0 signal 0 | |||
M_MIITXD2 | O | EMAC MII transmit data 2 | |||
M_SSI3FSS | I/O | SSI-3 frame | |||
M_MIITXD0 | O | EMAC MII transmit data 0 | |||
C_EQEP1B | I | Enhanced QEP-1 input B | |||
PH4_GPIO52 | U10 | I/O/Z | General-purpose input/output 52 | PU | 4 mA |
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
|||
M_EPI0S10 | I/O | EPI-0 signal 10 | |||
M_MIITXD1 | O | EMAC MII transmit data 1 | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
M_U3TX | O | UART-3 transmit data | |||
M_MIICOL | I | EMAC MII collision detect | |||
C_EQEP1S | I/O | Enhanced QEP-1 strobe | |||
PH5_GPIO53 | U9 | I/O/Z | General-purpose input/output 53 | PU | 4 mA |
M_EPI0S11 | I/O | EPI-0 signal 11 | |||
M_MIITXD0 | O | EMAC MII transmit data 0 | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
M_U3RX | I | UART-3 receive data | |||
M_MIIPHYRST | O | EMAC PHY MII reset | |||
C_EQEP1I | I/O | Enhanced QEP-1 index | |||
PH6_GPIO54 | R17 | I/O/Z | General-purpose input/output 54 | PU | 4 mA |
M_EPI0S26 | I/O | EPI-0 signal 26 | |||
M_MIIRXDV | I | EMAC MII receive data valid | |||
M_SSI1RX | I | SSI-1 receive data | |||
M_MIITXEN | O | EMAC MII transmit enable | |||
M_SSI0TX | O | SSI-0 transmit data | |||
M_MIIPHYINTR | I | EMAC PHY MII interrupt | |||
C_SPISIMOA | I/O | SPI-A slave in, master out | |||
C_EQEP3A | I | Enhanced QEP-1 input A | |||
PH7_GPIO55 | P18 | I/O/Z | General-purpose input/output 55 | PU | 4 mA |
M_MIIRXCK | I | EMAC MII receive clock | |||
M_EPI0S27 | I/O | EPI-0 signal 27 | |||
M_SSI1TX | O | SSI-1 transmit data | |||
M_MIITXCK | I | EMAC MII transmit clock | |||
M_SSI0RX | I | SSI-0 receive data | |||
M_MIIMDC | O | EMAC management data clock | |||
C_SPISOMIA | I/O | SPI-A master in, slave out | |||
C_EQEP3B | I | Enhanced QEP-3 input B | |||
PJ0_GPIO56 | W16 | I/O/Z | General-purpose input/output 56 | PU | 4 mA |
M_MIIRXER | I | EMAC MII receive error | |||
M_EPI0S16 | I/O | EPI-0 signal 16 | |||
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
M_SSI0CLK | I/O | SSI-0 clock | |||
M_MIIMDIO | I/O | EMAC management data input/output | |||
C_SPICLKA | I/O | SPI-A clock | |||
C_EQEP3S | I/O | Enhanced QEP-3 strobe | |||
PJ1_GPIO57 | V13 | I/O/Z | General-purpose input/output 57 | PU | 4 mA |
M_EPI0S17 | I/O | EPI-0 signal 17 | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
|||
M_I2C1SDA | I/OD | I2C-1 data open-drain bidirectional port | |||
M_MIIRXDV | I | EMAC MII receive data valid | |||
M_SSI0FSS | I/O | SSI-0 frame | |||
M_MIIRXD3 | I | EMAC MII receive data 3 | |||
C_SPISTEA | I/O | SPI-A slave transmit enable | |||
C_EQEP3I | I/O | Enhanced QEP-3 index | |||
PJ2_GPIO58 | V12 | I/O/Z | General-purpose input/output 58 | PU | 4 mA |
M_EPI0S18 | I/O | EPI-0 signal 18 | |||
M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
|||
M_MIIRXCK | I | EMAC MII receive clock | |||
M_SSI0CLK | I/O | SSI-0 clock | |||
M_U0TX | O | UART-0 transmit data | |||
M_MIIRXD2 | I | EMAC MII receive data 2 | |||
C_MCLKRA | I | McBSP-A receive clock | |||
C_EPWM7A | O | Enhanced PWM-7 output A | |||
PJ3_GPIO59 | U15 | I/O/Z | General-purpose input/output 59 | PU | 4 mA |
M_EPI0S19 | I/O | EPI-0 signal 19 | |||
M_CCP6 | I/O | Capture/Compare/PWM-6 (General-purpose Timer) |
|||
M_MIIMDC | O | EMAC management data clock | |||
M_SSI0FSS | I/O | SSI-0 frame | |||
M_U0RX | I | UART-0 receive data | |||
M_MIIRXD1 | I | EMAC MII receive data 1 | |||
C_MFSRA | I | McBSP-A receive frame sync | |||
C_EPWM7B | O | Enhanced PWM-7 output B | |||
PJ4_GPIO60 | V15 | I/O/Z | General-purpose input/output 60 | PU | 6 mA |
M_EPI0S28 | I/O | EPI-0 signal 28 | |||
M_CCP4 | I/O | Capture/Compare/PWM-4 (General-purpose Timer) |
|||
M_MIICOL | I | EMAC MII collision detect | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
M_MIIRXD0 | I | EMAC MII receive data 0 | |||
C_EPWM8A | O | Enhanced PWM-8 output A | |||
PJ5_GPIO61 | V14 | I/O/Z | General-purpose input/output 61 | PU | 6 mA |
M_EPI0S29 | I/O | EPI-0 signal 29 | |||
M_CCP2 | I/O | Capture/Compare/PWM-2 (General-purpose Timer) |
|||
M_MIICRS | I | EMAC MII carrier sense | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
M_MIIRXDV | I | EMAC MII receive data valid | |||
C_EPWM8B | O | Enhanced PWM-8 output B | |||
PJ6_GPIO62 | V16 | I/O/Z | General-purpose input/output 62 | PU | 6 mA |
M_EPI0S30 | I/O | EPI-0 signal 30 | |||
M_CCP1 | I/O | Capture/Compare/PWM-1 (General-purpose Timer) |
|||
M_MIIPHYINTR | I | EMAC PHY MII interrupt | |||
M_U2RX | I | UART-2 receive data | |||
M_MIIRXER | I | EMAC MII receive error | |||
C_EPWM9A | O | Enhanced PWM-9 output A | |||
PJ7_GPIO63 | H17 | I/O/Z | General-purpose input/output 63 | PU | 4 mA |
M_CCP0 | I/O | Capture/Compare/PWM-0 (General-purpose Timer) |
|||
M_MIIPHYRST | O | EMAC PHY MII reset | |||
M_U2TX | O | UART-2 transmit data | |||
M_MIIRXCK | I | EMAC MII receive clock | |||
M_XCLKIN | I | External oscillator input for USB PLL and CAN (always available, see Figure 6-16) | |||
C_EPWM9B | O | Enhanced PWM-9 output B | |||
PC0_GPIO64 | V4 | I/O/Z | General-purpose input/output 64 | PU | 4 mA |
M_EPI0S32(5) | I/O | EPI-0 signal 32 | |||
M_MIIRXD2 | I | EMAC MII receive data 2 | |||
C_EQEP1A | I | Enhanced QEP-1 input A | |||
C_EQEP2I | I/O | Enhanced QEP-2 index | |||
PC1_GPIO65 | W4 | I/O/Z | General-purpose input/output 65 | PU | 4 mA |
M_EPI0S33(5) | I/O | EPI-0 signal 33 | |||
M_MIICOL | I | EMAC MII collision detect | |||
C_EQEP1B | I | Enhanced QEP-1 input B | |||
C_EQEP2S | I/O | Enhanced QEP-2 strobe | |||
PC2_GPIO66 | U5 | I/O/Z | General-purpose input/output 66 | PU | 4 mA |
M_EPI0S37(5) | I/O | EPI-0 signal 37 | |||
M_MIITXEN | O | EMAC MII transmit enable | |||
C_EQEP1S | I/O | Enhanced QEP-1 strobe | |||
C_EQEP2A | I | Enhanced QEP-2 input A | |||
PC3_GPIO67 | V5 | I/O/Z | General-purpose input/output 67 | PU | 4 mA |
M_EPI0S36(5) | I/O | EPI-0 signal 36 | |||
M_MIITXCK | I | EMAC MII transmit clock | |||
C_EQEP1I | I/O | Enhanced QEP-1 index | |||
C_EQEP2B | I | Enhanced QEP-2 input B | |||
PC4_GPIO68 | W8 | I/O/Z | General-purpose input/output 68 | PU | 4 mA |
M_CCP5 | I | Capture/Compare/PWM-5 (General-purpose Timer) |
|||
M_MIITXD3 | O | EMAC MII transmit data 3 | |||
M_CCP2 | I | Capture/Compare/PWM-2 (General-purpose Timer) |
|||
M_CCP4 | I | Capture/Compare/PWM-4 (General-purpose Timer) |
|||
M_EPI0S2 | I/O | EPI-0 signal 2 | |||
M_CCP1 | I | Capture/Compare/PWM-1 (General-purpose Timer) |
|||
PC5_GPIO69 | W7 | I/O/Z | General-purpose input/output 69 | PU | 4 mA |
M_CCP1 | I | Capture/Compare/PWM-1 (General-purpose Timer) |
|||
M_CCP3 | I | Capture/Compare/PWM-3 (General-purpose Timer) |
|||
M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
|||
M_EPI0S3 | I/O | EPI-0 signal 3 | |||
PC6_GPIO70 | V8 | I/O/Z | General-purpose input/output 70 | PU | 4 mA |
M_CCP3 | I | Capture/Compare/PWM-3 (General-purpose Timer) |
|||
M_U1RX | I | UART-1 receive data | |||
M_CCP0 | I | Capture/Compare/PWM-0 (General-purpose Timer) |
|||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
|||
M_EPI0S4 | I/O | EPI-0 signal 4 | |||
PC7_GPIO71 | V9 | I/O/Z | General-purpose input/output 71 | PU | 4 mA |
M_CCP4 | I | Capture/Compare/PWM-4 (General-purpose Timer) |
|||
M_CCP0 | I | Capture/Compare/PWM-0 (General-purpose Timer) |
|||
M_U1TX | O | UART-1 transmit data | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
|||
M_EPI0S5 | I/O | EPI-0 signal 5 | |||
PK0_GPIO72 | K17 | I/O/Z | General-purpose input/output 72 | PU | 4 mA |
M_SSI0TX | O | SSI-0 transmit data | |||
C_SPISIMOA | I/O | SPI-A slave in, master out | |||
PK1_GPIO73 | N16 | I/O/Z | General-purpose input/output 73 | PU | 4 mA |
M_SSI0RX | I/O | SSI-0 receive data | |||
C_SPISOMIA | I/O | SPI-A master in, slave out | |||
PK2_GPIO74 | M16 | I/O/Z | General-purpose input/output 74 | PU | 4 mA |
M_SSI0CLK | I/O | SSI-0 clock | |||
C_SPICLKA | I/O | SPI-A clock | |||
PK3_GPIO75 | L18 | I/O/Z | General-purpose input/output 75 | PU | 4 mA |
M_SSI0FSS | I/O | SSI-0 frame | |||
C_SPISTEA | I/O | SPI-A slave transmit enable | |||
PK4_GPIO76 | U4 | I/O/Z | General-purpose input/output 76 | PU | 4 mA |
M_MIITXEN | O | EMAC MII transmit enable | |||
M_SSI0TX | O | SSI-0 transmit data | |||
PK5_GPIO77 | W3 | I/O/Z | General-purpose input/output 77 | PU | 4 mA |
M_MIITXCK | I | EMAC MII transmit clock | |||
M_SSI0RX | I/O | SSI-0 receive data | |||
PK6_GPIO78 | V2 | I/O/Z | General-purpose input/output 78 | PU | 4 mA |
M_MIITXER | O | EMAC MII transmit error | |||
M_SSI0CLK | I/O | SSI-0 clock | |||
PK7_GPIO79 | V3 | I/O/Z | General-purpose input/output 79 | PU | 4 mA |
M_MIICRS | I | EMAC MII carrier sense | |||
M_SSI0FSS | I/O | SSI-0 frame | |||
PL0_GPIO80 | U1 | I/O/Z | General-purpose input/output 80 | PU | 4 mA |
M_MIIRXD3 | I | EMAC MII receive data 3 | |||
M_SSI1TX | O | SSI-1 transmit data | |||
PL1_GPIO81 | U2 | I/O/Z | General-purpose input/output 81 | PU | 4 mA |
M_MIIRXD2 | I | EMAC MII receive data 2 | |||
M_SSI1RX | I/O | SSI-1 receive data | |||
PL2_GPIO82 | U3 | I/O/Z | General-purpose input/output 82 | PU | 4 mA |
M_MIIRXD1 | I | EMAC MII receive data 1 | |||
M_SSI1CLK | I/O | SSI-1 clock | |||
PL3_GPIO83 | T1 | I/O/Z | General-purpose input/output 83 | PU | 4 mA |
M_MIIRXD0 | I | EMAC MII receive data 0 | |||
M_SSI1FSS | I/O | SSI-1 frame | |||
PL4_GPIO84 | U18 | I/O/Z | General-purpose input/output 84 | PU | 4 mA |
M_MIICOL | I | EMAC MII collision detect | |||
M_SSI3TX | O | SSI-3 transmit data | |||
PL5_GPIO85 | T2 | I/O/Z | General-purpose input/output 85 | PU | 4 mA |
M_MIIPHYRST | O | EMAC PHY MII reset | |||
M_SSI3RX | I/O | SSI-3 receive data | |||
PL6_GPIO86 | T3 | I/O/Z | General-purpose input/output 86 | PU | 4 mA |
M_MIIPHYINTR | O | EMAC PHY MII interrupt | |||
M_SSI3CLK | I/O | SSI-3 clock | |||
PL7_GPIO87 | V18 | I/O/Z | General-purpose input/output 87 | PU | 4 mA |
M_MIIMDC | O | EMAC management data clock | |||
M_SSI3FSS | I/O | SSI-3 frame | |||
PM0_GPIO88 | R1 | I/O/Z | General-purpose input/output 88 | PU | 4 mA |
M_MIIMDIO | I/O | EMAC management data input/output | |||
M_SSI2TX | O | SSI-2 transmit data | |||
PM1_GPIO89 | R2 | I/O/Z | General-purpose input/output 89 | PU | 4 mA |
M_MIITXD3 | O | EMAC MII transmit data 3 | |||
M_SSI2RX | I/O | SSI-2 receive data | |||
PM2_GPIO90 | R3 | I/O/Z | General-purpose input/output 90 | PU | 4 mA |
M_MIITXD2 | O | EMAC MII transmit data 2 | |||
M_SSI2CLK | I/O | SSI-2 clock | |||
PM3_GPIO91 | P1 | I/O/Z | General-purpose input/output 91 | PU | 4 mA |
M_MIITXD1 | O | EMAC MII transmit data 1 | |||
M_SSI2FSS | I/O | SSI-2 frame | |||
PM4_GPIO92 | P2 | I/O/Z | General-purpose input/output 92 | PU | 4 mA |
M_MIITXD0 | O | EMAC MII transmit data 0 | |||
C_MDXA | O | McBSP-A transmit data | |||
PM5_GPIO93 | P3 | I/O/Z | General-purpose input/output 93 | PU | 4 mA |
M_MIIRXDV | I | EMAC MII receive data valid | |||
C_MDRA | I | McBSP-A receive data | |||
PM6_GPIO94 | P4 | I/O/Z | General-purpose input/output 94 | PU | 4 mA |
M_MIIRXER | I | EMAC MII receive error | |||
C_MCLKXA | O | McBSP-A transmit clock | |||
PM7_GPIO95 | N1 | I/O/Z | General-purpose input/output 95 | PU | 4 mA |
M_MIIRXCK | I | EMAC MII receive clock | |||
C_MFSXA | O | McBSP-A transmit frame sync | |||
PN0_GPIO96 | L17 | I/O/Z | General-purpose input/output 96 | PU | 4 mA |
M_I2C0SCL | I/OD | I2C-0 clock open-drain bidirectional port | |||
C_MCLKRA | I | McBSP-A receive clock | |||
PN1_GPIO97 | J17 | I/O/Z | General-purpose input/output 97 | PU | 4 mA |
M_I2C0SDA | I/OD | I2C-0 data open-drain bidirectional port | |||
C_MFSRA | I | McBSP-A receive frame sync | |||
PN2_GPIO98 | J18 | I/O/Z | General-purpose input/output 98 | PU | 4 mA |
M_U1RX | I | UART-1 receive data | |||
PN3_GPIO99 | G18 | I/O/Z | General-purpose input/output 99 | PU | 4 mA |
M_U1TX | O | UART-1 transmit data | |||
PN4_GPIO100 | F18 | I/O/Z | General-purpose input/output 100 | PU | 4 mA |
M_U3TX | O | UART-3 transmit data | |||
PN5_GPIO101 | H16 | I/O/Z | General-purpose input/output 101 | PU | 4 mA |
M_U3RX | I | UART-3 receive data | |||
PN6_GPIO102 | R18 | I/O/Z | General-purpose input/output 102 | PU | 4 mA |
M_U4RX | I | UART-4 receive data | |||
M_EPI0S42(5) | I/O | EPI-0 signal 42 | |||
M_USB0EPEN | O | USB-0 external power enable (optionally used in the host mode) |
|||
PN7_GPIO103 | T17 | I/O/Z | General-purpose input/output 103 | PU | 4 mA |
M_U4TX | O | UART-4 transmit data | |||
M_EPI0S43(5) | I/O | EPI-0 signal 43 | |||
M_USB0PFLT | I | USB-0 external power error state (optionally used in the host mode) |
|||
PP0_GPIO104 | G17 | I/O/Z | General-purpose input/output 104 | PU | 4 mA |
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
C_I2CSDAA | I/OD | I2C-A data open-drain bidirectional port | |||
PP1_GPIO105 | G16 | I/O/Z | General-purpose input/output 105 | PU | 4 mA |
M_I2C1SDA | I/OD | I2C-1 data open-drain bidirectional port | |||
C_I2CSCLA | I/OD | I2C-A clock open-drain bidirectional port | |||
PP2_GPIO106 | F17 | I/O/Z | General-purpose input/output 106 | PU | 4 mA |
M_I2C0SCL | I/OD | I2C-0 clock open-drain bidirectional port | |||
C_EQEP1A | I | Enhanced QEP-1 input A | |||
PP3_GPIO107 | E18 | I/O/Z | General-purpose input/output 107 | PU | 4 mA |
M_I2C0SDA | I/OD | I2C-0 data open-drain bidirectional port | |||
C_EQEP1B | I | Enhanced QEP-1 input B | |||
PP4_GPIO108 | C19 | I/O/Z | General-purpose input/output 108 | PU | 4 mA |
M_I2C1SCL | I/OD | I2C-1 clock open-drain bidirectional port | |||
C_EQEP1S | I/O | Enhanced QEP-1 strobe | |||
PP5_GPIO109 | C18 | I/O/Z | General-purpose input/output 109 | PU | 4 mA |
M_I2C1SDA | I/OD | I2C-1 data open-drain bidirectional port | |||
C_EQEP1I | I/O | Enhanced QEP-1 index | |||
PP6_GPIO110 | C17 | I/O/Z | General-purpose input/output 110 | PU | 4 mA |
C_EQEP2A | I | Enhanced QEP-2 input A | |||
C_EQEP3S | I/O | Enhanced QEP-3 strobe | |||
PP7_GPIO111 | B18 | I/O/Z | General-purpose input/output 111 | PU | 4 mA |
C_EQEP2B | I | Enhanced QEP-2 input B | |||
C_EQEP3I | I/O | Enhanced QEP-3 index | |||
PQ0_GPIO112 | C16 | I/O/Z | General-purpose input/output 112 | PU | 4 mA |
C_EQEP2I | I/O | Enhanced QEP-2 index | |||
C_EQEP3A | I | Enhanced QEP-1 input A | |||
PQ1_GPIO113 | C6 | I/O/Z | General-purpose input/output 113 | PU | 4 mA |
C_EQEP2S | I/O | Enhanced QEP-2 strobe | |||
C_EQEP3B | I | Enhanced QEP-3 input B | |||
PQ2_GPIO114 | C5 | I/O/Z | General-purpose input/output 114 | PU | 4 mA |
M_U0RX | I | UART-0 receive data | |||
PQ3_GPIO115 | C4 | I/O/Z | General-purpose input/output 115 | PU | 4 mA |
M_U0TX | O | UART-0 transmit data | |||
PQ4_GPIO116 | C3 | I/O/Z | General-purpose input/output 116 | PU | 4 mA |
M_SSI1TX | O | SSI-1 transmit data | |||
PQ5_GPIO117 | C2 | I/O/Z | General-purpose input/output 117 | PU | 4 mA |
M_SSI1RX | I | SSI-1 receive data | |||
PQ6_GPIO118 | D3 | I/O/Z | General-purpose input/output 118 | PU | 4 mA |
C_SCITXDA | O | SCI-A transmit data | |||
PQ7_GPIO119 | D2 | I/O/Z | General-purpose input/output 119 | PU | 4 mA |
C_SCIRXDA | I | SCI-A receive data | |||
PR0_GPIO120 | N18 | I/O/Z | General-purpose input/output 120 | PU | 4 mA |
M_SSI3TX | O | SSI-3 transmit data | |||
PR1_GPIO121 | M18 | I/O/Z | General-purpose input/output 121 | PU | 4 mA |
M_SSI3RX | I | SSI-3 receive data | |||
PR2_GPIO122 | K18 | I/O/Z | General-purpose input/output 122 | PU | 4 mA |
M_SSI3CLK | I/O | SSI-3 clock | |||
PR3_GPIO123 | M17 | I/O/Z | General-purpose input/output 123 | PU | 4 mA |
M_SSI3FSS | I/O | SSI-3 frame | |||
PR4_GPIO124 | J3 | I/O/Z | General-purpose input/output 124 | PU | 4 mA |
C_EPWM7A | O | Enhanced PWM-7 output A | |||
PR5_GPIO125 | J2 | I/O/Z | General-purpose input/output 125 | PU | 4 mA |
C_EPWM7B | O | Enhanced PWM-7 output B | |||
PR6_GPIO126 | J1 | I/O/Z | General-purpose input/output 126 | PU | 4 mA |
C_EPWM8A | O | Enhanced PWM-8 output A | |||
PR7_GPIO127 | K3 | I/O/Z | General-purpose input/output 127 | PU | 4 mA |
C_EPWM8B | O | Enhanced PWM-8 output B | |||
PS0_GPIO128 | K2 | I/O/Z | General-purpose input/output 128 | PU | 4 mA |
C_EPWM9A | O | Enhanced PWM-9 output A | |||
PS1_GPIO129 | L3 | I/O/Z | General-purpose input/output 129 | PU | 4 mA |
C_EPWM9B | O | Enhanced PWM-9 output B | |||
PS2_GPIO130 | L2 | I/O/Z | General-purpose input/output 130 | PU | 4 mA |
C_EPWM10A | O | Enhanced PWM-10 output A | |||
PS3_GPIO131 | M3 | I/O/Z | General-purpose input/output 131 | PU | 4 mA |
C_EPWM10B | O | Enhanced PWM-10 output B | |||
PS4_GPIO132 | M2 | I/O/Z | General-purpose input/output 132 | PU | 4 mA |
C_EPWM11A | O | Enhanced PWM-11 output A | |||
PS5_GPIO133 | M1 | I/O/Z | General-purpose input/output 133 | PU | 4 mA |
C_EPWM11B | O | Enhanced PWM-11 output B | |||
PS6_GPIO134 | N3 | I/O/Z | General-purpose input/output 134 | PU | 4 mA |
C_EPWM12A | O | Enhanced PWM-12 output A | |||
PS7_GPIO135 | N2 | I/O/Z | General-purpose input/output 135 | PU | 4 mA |
C_EPWM12B | O | Enhanced PWM-12 output B | |||
Resets | |||||
XRS | C1 | I/OD | Digital Subsystem Reset (in) and Watchdog/Power-on Reset (out). In most applications, TI recommends that the XRS pin be tied with the ARS pin. The Digital Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Digital Subsystem. This pin is also driven low by the Digital Subsystem when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If needed, an external circuitry may also drive this pin to assert device reset. In this case, TI recommends that this pin be driven by an open-drain device. A noise filtering circuit can be connected to this pin. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the Digital Subsystem to terminate execution. The Cortex-M3 program counter points to the address contained at the location 0x00000004. The C28 program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. | PU | 4 mA |
ARS | A3 | I/OD | Analog Subsystem Reset (in) and Power-on Reset (out). TI recommends that the ARS pin be tied with the XRS pin. The Analog Subsystem has a built-in POR circuit, and during a power-on condition, this pin is driven low by the Analog Subsystem. If needed, external circuitry may also drive this pin to assert a device reset. In this case, TI recommends that this pin be driven by an open-drain device. Regardless of the source, the Analog Subsystem reset causes the digital logic associated with the Analog Subsystem, to enter reset state. The output buffer of this pin is an open-drain with an internal pullup. | PU | 4 mA |
Clocks | |||||
X1 | J19 | I | External oscillator input or on-chip crystal-oscillator input. To use the on-chip oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. See Figure 6-7. | ||
X2 | G19 | O | On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. See Figure 6-7. | ||
VSSOSC | H18 | Clock Oscillator Ground Pin. Use this pin to connect the GND of external crystal load capacitors or the ground pin of 3-terminal ceramic resonators with built-in capacitors. Do not connect to board ground. See Figure 6-7. | |||
VSSOSC | H19 | Clock Oscillator Ground Pin. Use this pin to connect the GND of external crystal load capacitors or the ground pin of 3-terminal ceramic resonators with built-in capacitors. Do not connect to board ground. See Figure 6-7. | |||
XCLKIN | see PJ7_GPIO63 | I | External oscillator input. This pin feeds a clock from an external 3.3-V oscillator to internal USB PLL module and to the CAN peripherals. | ||
XCLKOUT | see PF2_GPIO34 | O/Z | External oscillator output. This pin outputs a clock divided-down from the internal PLL System Clock. The divide ratio is defined in the XPLLCLKCFG register. | ||
Boot Pins | |||||
BOOT_0 | see PG3_GPIO43 | I | One of four boot mode pins. BOOT_0 selects a specific configuration source from which the Concerto device boots on start-up. | PU | |
BOOT_1 | see PG7_GPIO47 | I | One of four boot mode pins. BOOT_1 selects a specific configuration source from which the Concerto device boots on start-up. | PU | |
BOOT_2 | see PF3_GPIO35 | I | One of four boot mode pins. BOOT_2 selects a specific configuration source from which the Concerto device boots on start-up. | PU | |
BOOT_3 | see PF2_GPIO34 | I | One of four boot mode pins. BOOT_3 selects a specific configuration source from which the Concerto device boots on start-up. | PU | |
JTAG | |||||
TRST | N19 | I | JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-low test pin and must be maintained low during normal device operation. An external pull-down resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. | PD | |
TCK | L19 | I | JTAG test clock | ||
TMS | M19 | I | JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. | PU | |
TDI | K19 | I | JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. | PU | |
TDO | T19 | O | JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. | 4 mA | |
EMU0 | P19 | I/O/Z | Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator to connect to the device and to modify FLASH contents. |
PU | 4 mA |
EMU1 | R19 | I/O/Z | Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator to connect to the device and to modify FLASH contents. |
PU | 4 mA |
ITM Trace (ARM Instrumentation Trace Macrocell) | |||||
TRACED0 | see PF3_GPIO35 | O | ITM Trace data 0 | 4 mA | |
TRACED1 | see PG3_GPIO43 | O | ITM Trace data 1 | 4 mA | |
TRACED2 | see PF0_GPIO32 | O | ITM Trace data 2 | 4 mA | |
TRACED3 | see PF1_GPIO33 | O | ITM Trace data 3 | 4 mA | |
TRACECLK | see PF2_GPIO34 | O | ITM Trace clock | 4 mA | |
Test Pins | |||||
FLT1 | K1 | I/O | FLASH Test Pin 1. Reserved for TI. Must be left unconnected. | ||
FLT2 | L1 | I/O | FLASH Test Pin 2. Reserved for TI. Must be left unconnected. | ||
Internal Voltage Regulator Control | |||||
VREG18EN | A15 | Internal 1.8-V VREG Enable/Disable for VDD18. Pull low to enable the internal 1.8-V voltage regulator (VREG18), pull high to disable VREG18. | PD | ||
VREG12EN | E19 | Internal 1.2-V VREG Enable/Disable for VDD12. Pull low to enable the internal 1.2-V voltage regulator (VREG12), pull high to disable VREG12. | PD | ||
Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators | |||||
VDDIO | D4 | 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. When the 1.2-V VREG is enabled (by pulling the VREG12EN pin low), these pins also supply power to the Digital Subsystem. When the 1.8-V VREG is enabled (by pulling the VREG18EN pin low), these pins also supply power to the Analog Subsystem. | |||
VDDIO | D5 | ||||
VDDIO | D15 | ||||
VDDIO | D16 | ||||
VDDIO | G7 | ||||
VDDIO | G13 | ||||
VDDIO | G8 | ||||
VDDIO | G9 | ||||
VDDIO | G10 | ||||
VDDIO | G11 | ||||
VDDIO | G12 | ||||
VDDIO | H7 | ||||
VDDIO | H13 | ||||
VDDIO | J7 | ||||
VDDIO | J13 | ||||
VDDIO | N8 | ||||
VDDIO | N9 | ||||
VDDIO | N10 | ||||
VDDIO | N11 | ||||
VDDIO | K7 | ||||
VDDIO | L7 | ||||
VDDIO | K13 | ||||
VDDIO | L13 | ||||
VDDIO | T4 | ||||
VDDIO | T5 | ||||
VDDIO | T7 | ||||
VDDIO | T8 | ||||
VDDIO | T15 | ||||
VDDIO | T16 | ||||
VDDIO | T13 | ||||
VDDIO | U13 | ||||
Digital Logic Power Pins (Analog Subsystem) | |||||
VDD18 | C7 | 1.8-V Digital Logic Power Pins (associated with the Analog Subsystem) - no supply needed when using internal VREG18. Tie with 1.2-µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. | |||
VDD18 | D7 | ||||
VDD18 | D12 | ||||
VDD18 | D13 | ||||
Digital Logic Power Pins (Master and Control Subsystems) | |||||
VDD12 | M7 | 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 250-nF (minimum) to 750-nF (maximum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. | |||
VDD12 | M13 | ||||
VDD12 | N7 | ||||
VDD12 | N12 | ||||
VDD12 | N13 | ||||
VDD12 | T10 | ||||
VDD12 | T11 | ||||
VDD12 | T12 | ||||
Digital Logic Ground (Analog, Master, and Control Subsystems) | |||||
VSS | A1 | Digital Ground | |||
VSS | A2 | ||||
VSS | A18 | ||||
VSS | A19 | ||||
VSS | B1 | ||||
VSS | B19 | ||||
VSS | D6 | ||||
VSS | D14 | ||||
VSS | E4 | ||||
VSS | E16 | ||||
VSS | H8 | ||||
VSS | H9 | ||||
VSS | H10 | ||||
VSS | H11 | ||||
VSS | H12 | ||||
VSS | J4 | ||||
VSS | J8 | ||||
VSS | J9 | ||||
VSS | J10 | ||||
VSS | J11 | ||||
VSS | J12 | ||||
VSS | J16 | ||||
VSS | K4 | ||||
VSS | K8 | ||||
VSS | K9 | ||||
VSS | K10 | ||||
VSS | K11 | ||||
VSS | K12 | ||||
VSS | K16 | ||||
VSS | L4 | Digital Ground | |||
VSS | L8 | ||||
VSS | L9 | ||||
VSS | L10 | ||||
VSS | L11 | ||||
VSS | L12 | ||||
VSS | L16 | ||||
VSS | M8 | ||||
VSS | M9 | ||||
VSS | M10 | ||||
VSS | M11 | ||||
VSS | M12 | ||||
VSS | R4 | ||||
VSS | R16 | ||||
VSS | T6 | ||||
VSS | T9 | ||||
VSS | T14 | ||||
VSS | V1 | ||||
VSS | V19 | ||||
VSS | W1 | ||||
VSS | W2 | ||||
VSS | W18 | ||||
VSS | W19 |