ZHCSBK0D October   2012  – October 2015 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 描述
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics
    5. 5.5  Power Consumption Summary
    6. 5.6  Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
    7. 5.7  Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
        4. 5.9.2.4 Internal Clock Frequencies
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing - Master Subsystem
      5. 5.9.5 Flash Timing - Control Subsystem
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
        2. 5.9.6.2 GPIO - Input Timing
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
      7. 5.9.7 External Interrupt Electrical Data and Timing
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
        4. 5.11.6.4 MDIO Electrical Data and Timing
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. 5.12.1.2.1 Trip-Zone Input Timing
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
          2. 5.12.6.2.2 SPI Slave Mode Timing
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem's Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem's Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems' Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 Development Tools
      1. 7.1.1 H63C2 Concerto Experimenter Kit
      2. 7.1.2 F28M36 Concerto Control Card
    2. 7.2 Software Tools
      1. 7.2.1 controlSUITE
      2. 7.2.2 Code Composer Studio (CCS) Integrated Development Environment (IDE)
      3. 7.2.3 F021 Flash Application Programming Interface (API)
    3. 7.3 Training
  8. 8器件和文档支持
    1. 8.1 器件支持
      1. 8.1.1 开发支持
      2. 8.1.2 器件和开发支持工具命名规则
    2. 8.2 文档支持
      1. 8.2.1 相关文档
      2. 8.2.2 接收文档更新通知
    3. 8.3 相关链接
    4. 8.4 社区资源
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Glossary
  9. 9机械、封装和可订购信息
    1. 9.1 封装信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZWT|289
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 修订历史记录

Changes from February 28, 2014 to October 29, 2015 (from C Revision (February 2014) to D Revision)

  • 全局：已更新温度选项。Go
  • 全局：仅 F28M36P63C2 器件具有 Q 温度范围。Go
  • 全局：已将“CAN 2.0”改为“ISO11898-1 (CAN 2.0B)”Go
  • 全局：限制文档Go
  • 全局：已删除 MICROWIREGo
  • 全局：已将“Philips® I2C 总线规范第 2.1 版”替换为“NXP® I2C 总线规范和用户手册 (UM10204)”。Go
  • Section 1.1 (特性）：已删除“Cortex-M3 内核硬件内置自检”特性。Go
  • Section 1.1：已更新“控制器局域网 (CAN)”特性。Go
  • 已添加“温度选项”特性。Go
  • Table 3-1 (Device Comparison): Changed title from "Hardware Features" to "Device Comparison". Go
  • Table 3-1: Updated temperature options. Go
  • Table 3-1: The Q temperature range is available only on the F28M36P63C2 device.Go
  • Table 3-1: Updated package availability. Go
  • Table 3-1: Removed "Product status" row and associated footnote. Go
  • Table 3-1: Added "FPU" row under "Control Subsystem — C28x"Go
  • Table 3-1: Added "VCU" row under "Control Subsystem — C28x"Go
  • Table 3-1: Added footnote about CAN. Go
  • Table 3-1: Added footnote about EPI. Go
  • Section 4 (Terminal Configuration and Functions): Changed title from "Terminal Description" to "Terminal Configuration and Functions". Go
  • Section 4.2 (Signal Descriptions): Changed title from "Terminal Functions" to "Signal Descriptions". Go
  • Table 4-1 (Signal Descriptions): Changed title from "Terminal Functions" to "Signal Descriptions". Go
  • Table 4-1: Updated DESCRIPTION of PF6_GPIO38, PG6_GPIO46, XRS, and ARS. Go
  • Section 5 (Specifications): Changed title from "Device Operating Conditions" to "Specifications". Go
  • Section 5.1 (Absolute Maximum Ratings): Moved Storage temperature (Tstg) from Section 5.2 to "Absolute Maximum Ratings" sectionGo
  • Section 5.2 (ESD Ratings): Changed section title from "Handling Ratings" to "ESD Ratings" Go
  • Section 5.2: Updated sectionGo
  • Section 5.3 (Recommended Operating Conditions): Moved VIL, VIH, IOL, and IOH to Section 5.4. Go
  • Section 5.3: Updated temperature ranges. Go
  • Section 5.3: Added footnote referencing the Calculating Useful Lifetimes of Embedded Processors Application Report (SPRABX4).Go
  • Section 5.4 (Electrical Characteristics): Added VIL, VIH, IOL, and IOH. Go
  • Section 5.5 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power Consumption Summary". Go
  • Table 5-1 (Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK): Updated MAX IDDIO values for SLEEP IDLE mode, SLEEP STANDBY mode, and DEEP SLEEP STANDBY mode.Go
  • Table 5-2 (Current Consumption at 125-MHz C28x SYSCLKOUT and 125-MHz M3SSCLK): Updated MAX IDDIO values for SLEEP IDLE mode, SLEEP STANDBY mode, and DEEP SLEEP STANDBY mode.Go
  • Section 5.9 (Timing and Switching Characteristics): Added section. Go
  • Section 5.9.1 (Power Sequencing): Removed "(for analog pins, this value is 0.7 V above VDDA)" from "There is no power sequencing requirement needed ..." paragraph.Go
  • Figure 5-1 (Power-On Reset): Updated tw(RSL1). Added tw(RSL2). Go
  • Figure 5-1: Updated footnote about XRS pin. Go
  • Table 5-3 (Reset (XRS) Timing Requirements): Updated description of tw(RSL2). Go
  • Table 5-4 (Reset (XRS) Switching Characteristics): tOSCST: Removed MIN value of 1 ms. Changed TYP value from 10 ms to 2 ms. Go
  • Section 5.9.1.1 (Power Management and Supervisory Circuit Solutions): Removed "Power Management and Supervisory Circuit Solutions" table (Table 6-15 in SPRS825C). Go
  • Section 5.9.2.1 (Changing the Frequency of the Main PLL): Updated section. Go
  • Table 5-7 (Crystal Oscillator Electrical Characteristics): Added table. Go
  • Table 5-12 (PLL Lock Times): Updated footnote. Go
  • Section 5.9.4 (Flash Timing – Master Subsystem): Removed "Master Subsystem – Flash/OTP Endurance for T Temperature Material" table (Table 6-16 in SPRS825C).Go
  • Section 5.9.4: Removed "Master Subsystem – Flash/OTP Endurance for S Temperature Material" table (Table 6-17 in SPRS825C). Go
  • Section 5.9.4: Removed "Master Subsystem – Flash Parameters at 125 MHz" table (Table 6-20 in SPRS825C). Go
  • Table 5-16 (Master Subsystem – Flash/OTP Endurance): Changed title from "Master Subsystem – Flash/OTP Endurance for Q Temperature Material" to "Master Subsystem – Flash/OTP Endurance". Go
  • Table 5-16: Removed "ERASE/PROGRAM TEMPERATURE" column. Go
  • Table 5-16: Removed footnote. Go
  • Table 5-17 (Master Subsystem – Flash Parameters): Changed title from "Master Subsystem – Flash Parameters at 75 MHz" to "Master Subsystem – Flash Parameters". Go
  • Table 5-17: Updated table. Go
  • Table 5-17: Updated "Program time includes overhead ..." footnoteGo
  • Table 5-17: Added footnote about current and Flash APIGo
  • Section 5.9.5 (Flash Timing – Control Subsystem): Removed "Control Subsystem – Flash/OTP Endurance for T Temperature Material" table (Table 6-24 in SPRS825C). Go
  • Section 5.9.5: Removed "Control Subsystem – Flash/OTP Endurance for S Temperature Material" table (Table 6-25 in SPRS825C). Go
  • Section 5.9.5: Removed "Control Subsystem – Flash Parameters at 150 MHz" table (Table 6-28 in SPRS825C). Go
  • Table 5-21 (Control Subsystem – Flash/OTP Endurance): Changed title from "Control Subsystem – Flash/OTP Endurance for Q Temperature Material" to "Control Subsystem – Flash/OTP Endurance". Go
  • Table 5-21: Removed "ERASE/PROGRAM TEMPERATURE" column. Go
  • Table 5-21: Removed footnote. Go
  • Table 5-22 (Control Subsystem – Flash Parameters): Changed title from "Control Subsystem – Flash Parameters at 100 MHz" to "Control Subsystem – Flash Parameters". Go
  • Table 5-22: Updated table. Go
  • Table 5-22: Updated "Program time includes overhead ..." footnote. Go
  • Table 5-22: Added footnote about current and Flash API, Go
  • Section 5.11.4 (Cortex-M3 Controller Area Network): Added NOTE about CAN and D_CAN. Go
  • Section 5.12.7.1.2 (McBSP as SPI Master or Slave Timing): Replaced "For all SPI slave modes ..." paragraphs with "For all SPI slave modes ..." table footnotes. Go
  • Table 5-81 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Added "For all SPI slave modes ..." footnote. Go
  • Table 5-83 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Added "For all SPI slave modes ..." footnote. Go
  • Table 5-85 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Added "For all SPI slave modes ..." footnote. Go
  • Table 5-87 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Added "For all SPI slave modes ..." footnote. Go
  • Table 6-2 (Control Subsystem Peripheral Frame 0): Changed title from "Control Subsystem Peripheral Frame 0 (Includes Analog)" to "Control Subsystem Peripheral Frame 0". Go
  • Table 6-2: 0000 1780 – 0000 17FF: Changed register name from "C Hardware Logic BIST Registers" to "Hardware BIST Registers".Go
  • Table 6-10 (Master Subsystem Peripherals): 400F B000 – 400F B1FF: Changed "PBIST Control Registers" to "Reserved". Go
  • Table 6-10: 400F BB00 – 400F BBFF: Changed "M HWBIST Registers" to "Reserved". Go
  • Section 6.2 (Identification): Added section. Go
  • Table 6-14 (Interrupts from NVIC to Cortex-M3): Interrupt Number 91: Changed "PBIST Done" to "Reserved". Go
  • Section 6.4.2 (C28x Core Hardware Built-In Self-Test): Updated section. Go
  • Section 6.9.3 (Analog and Digital Subsystems' Power-On-Reset Functionality): Added statement clarifying that POR is always enabled. Go
  • Figure 6-7 (Connecting Input Clocks to a Concerto Device): Updated figureGo
  • Section 6.10.3 (External Oscillators (Pins X1, VSSOSC, XCLKIN)): Updated sectionGo
  • Section 6.10.4 (Main PLL): Changed the maximum Main PLL output clock from 550 MHz to 300 MHz. Go
  • Figure 6-8 (Main PLL): Changed the maximum Main PLL output clock from 550 MHz to 300 MHz. Go
  • Section 6.12.3 (C28x STANDBY Mode): Changed MTOCIPCINT1 to MTOCIPCINT2Go
  • Table 6-31 (AIO_MUX1 Pin Assignments (C28x AIO Modes)): Changed ADC2INB2 to ADC1INB2 in Device Pin Name column and C28x AIO Mode 1 columnGo
  • Table 6-31: Changed ADC2INB6 to ADC1INB6 in Device Pin Name column and C28x AIO Mode 1 columnGo
  • Section 7 (Applications, Implementation, and Layout): Added section. Go
  • Figure 8-1 （器件命名规则）：已更新“温度范围”。Go
  • Section 8.2.1 （相关文档）：已添加参考文档。Go
  • Section 8.2.2 （接收文档更新通知）：新增了章节。Go
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