ZHCSBK0D October   2012  – October 2015 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 描述
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics
    5. 5.5  Power Consumption Summary
    6. 5.6  Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
    7. 5.7  Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
        4. 5.9.2.4 Internal Clock Frequencies
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing - Master Subsystem
      5. 5.9.5 Flash Timing - Control Subsystem
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
        2. 5.9.6.2 GPIO - Input Timing
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
      7. 5.9.7 External Interrupt Electrical Data and Timing
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
        4. 5.11.6.4 MDIO Electrical Data and Timing
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. 5.12.1.2.1 Trip-Zone Input Timing
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
          2. 5.12.6.2.2 SPI Slave Mode Timing
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem's Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem's Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems' Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 Development Tools
      1. 7.1.1 H63C2 Concerto Experimenter Kit
      2. 7.1.2 F28M36 Concerto Control Card
    2. 7.2 Software Tools
      1. 7.2.1 controlSUITE
      2. 7.2.2 Code Composer Studio (CCS) Integrated Development Environment (IDE)
      3. 7.2.3 F021 Flash Application Programming Interface (API)
    3. 7.3 Training
  8. 8器件和文档支持
    1. 8.1 器件支持
      1. 8.1.1 开发支持
      2. 8.1.2 器件和开发支持工具命名规则
    2. 8.2 文档支持
      1. 8.2.1 相关文档
      2. 8.2.2 接收文档更新通知
    3. 8.3 相关链接
    4. 8.4 社区资源
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Glossary
  9. 9机械、封装和可订购信息
    1. 9.1 封装信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZWT|289
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Device Comparison

Table 3-1 lists the features of the F28M36x devices.

Table 3-1 Device Comparison

FEATURE TYPE(1) P63C2 P53C2 H53C2 H53B2 H33C2 H33B2
Master Subsystem — ARM Cortex-M3
Speed (MHz)(2) – 125 125 100 100 100 100
Flash (KB) – 1024 512 512 512 512 512
RAM ECC (KB) – 16 16 16 16 16 16
RAM Parity (KB) – 112 112 112 112 112 112
IPC Message RAM Parity (KB) – 2 2 2 2 2 2
Security Zones – 2 2 2 2 2 2
10/100 ENET 1588 MII 0 Yes Yes Yes No Yes No
USB OTG FS 0 Yes Yes Yes No Yes No
SSI/SPI 0 4 4 4 4 4 4
UART 0 5 5 5 5 5 5
I2C 0 2 2 2 2 2 2
CAN(3) 0 2 2 2 2 2 2
µDMA 0 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch
EPI(4) 0 1 1 1 1 1 1
µCRC module 0 1 1 1 1 1 1
General-Purpose Timers – 4 4 4 4 4 4
Watchdog Timer modules – 2 2 2 2 2 2
Control Subsystem — C28x
Speed (MHz)(2) 150 150 150 150 150 150
FPU Yes
VCU Yes
Flash (KB) 512 512 512 512 512 512
RAM ECC (KB) 20 20 20 20 20 20
RAM Parity (KB) 16 16 16 16 16 16
IPC Message RAM Parity (KB) 2 2 2 2 2 2
Security Zones 1 1 1 1 1 1
ePWM modules 2 12: 24 outputs
High-Resolution Pulse Width Modulator (HRPWM) outputs 2 16 outputs
eCAP modules/PWM outputs 0 6 (32-bit)
eQEP modules 0 3 (32-bit)
Fault Trip Zones – 12 on any of 64 GPIO pins
McBSP/SPI 1 1 1 1 1 1 1
SCI 0 1 1 1 1 1 1
SPI 0 1 1 1 1 1 1
I2C 0 1 1 1 1 1 1
DMA 0 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch
EPI(4) 0 1 1 1 1 1 1
32-Bit Timers – 3 3 3 3 3 3
Shared
Supplemental RAM Parity (KB) 64 64 64 64 0 0
12-Bit ADC 1 MSPS(5) 3 2.88 2.88 2.88 2.88 2.88 2.88
Conversion Time(5) 347 ns 347 ns 347 ns 347 ns 347 ns 347 ns
Channels 12 12 12 12 12 12
Sample-and-Hold 2 2 2 2 2 2
12-Bit ADC 2 MSPS(5) 3 2.88 2.88 2.88 2.88 2.88 2.88
Conversion Time(5) 347 ns 347 ns 347 ns 347 ns 347 ns 347 ns
Channels 12 12 12 12 12 12
Sample-and-Hold 2 2 2 2 2 2
Comparators with Integrated DACs 0 6 6 6 6 6 6
Voltage Regulator Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC)
Clocking See Section 6.10
Additional Safety
Master Subsystem 2 Watchdogs, NMI Watchdog: CPU, Memory
Control Subsystem NMI Watchdog: CPU, Memory
Shared Critical Register and I/O Function Lock Protection; RAM Fetch Protection
Packaging
Package Type 289-Ball ZWT New Fine Pitch Ball Grid Array Yes Yes Yes Yes Yes Yes
Junction Temperature (TJ) T: –40°C to 105°C – Yes Yes Yes Yes Yes Yes
S: –40°C to 125°C – Yes Yes Yes Yes Yes Yes
Q: –40°C to 150°C(6) – Yes No No No No No
Free-Air Temperature (TA) Q: –40°C to 125°C(6) – Yes No No No No No
  1. A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) and in the peripheral reference guides.
  2. The maximum frequency at which the Cortex-M3 core can run is 125 MHz. The clock divider before the Cortex-M3 core can only take values of /1, /2, or /4. For this reason, when the C28x is configured to run at the maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 is 75 MHz. If the Cortex-M3 is configured to run at 125 MHz, the maximum frequency of the C28x is limited to 125 MHz. If the Cortex-M3 is configured to run at 100 MHz, the maximum frequency of the C28x is limited to 100 MHz.
  3. The CAN module uses the popular IP known as D_CAN. This document uses the names “CAN” and “D_CAN” interchangeably to reference this peripheral.
  4. Single EPI arbitrated between masters in Master and Control Subsystems.
  5. An integer divide ratio must be maintained between the C28x and ADC clock frequencies. All MSPS and Conversion Time values are based on the maximum C28x clock frequency.
  6. "Q" refers to Q100 qualification for automotive applications.

Table 3-2 Possible Speed Combinations for Cortex-M3 and C28x Cores

Cortex-M3 75 MHz 125 MHz 100 MHz
C28x 150 MHz 125 MHz 100 MHz
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