8.3.1 The Shield

The FDC1004Q measures capacitance between CINn and ground. That means any capacitance to ground on signal path between the FDC1004Q CINn pins and sensor is included in the FDC1004Q conversion result.

In some applications, the parasitic capacitance of the sensor connections can be larger than the capacitance of the sensor. If that parasitic capacitance is stable, it can be treated as a constant capacitive offset. However, the parasitic capacitance of the sensor connections can have significant variation due to environmental changes (such as mechanical movement, temperature shifts, humidity changes). These changes are seen as drift in the conversion result and may significantly compromise the system accuracy.

To eliminate the CINn parasitic capacitance to ground, the FDC1004Q SHLDx signals can be used for shielding the connection between the sensor and CINn. The SHLDx output is the same signal waveform as the excitation of the CINn pin; the SHLDx is driven to the same voltage potential as the CINn pin. Therefore, there is no current between CINn and SHLDx pins, and any capacitance between these pins does not affect the CINn charge transfer. Ideally, the CINn to SHLD capacitance does not have any contribution to the FDC1004Q result.

In differential measurements, SHLD1 is assigned to CHn and SHLD2 is assigned to CHm, where n < m. For instance in the measurement CIN1 – CIN2, where CHA = CIN1 and CHB = CIN2 (see Table 4), SHDL1 is assigned to CIN1 and SHDL2 is assigned to CIN2.

In a single ended configuration, such as CINn vs. GND, SHLD1 is internally shorted to SHLD2. In a single ended configuration, such as CINn vs. GND with CAPDAC enabled, SHLD1 is assigned to the selected channel, SHLD2 is floating.

For best results, locate the FDC1004Q as close as possible to the capacitive sensor. Minimize the connection length between the sensor and FDC1004Q CINn pins and between the sensor ground and the FDC1004Q GND pin. Shield the PCB traces to the CINn pins and connect the shielding to the FDC1004Q SHLDx pins. In addition, if a shielded cable is used to connect the FDC1004Q to the sensor, the shield should be connected to the appropriate SHLDx pin. In applications where only one SHLDx pin is used, the unused SHLDx pin can be left unconnected.

For more information on how to design a sensor with a shield, refer to Capacitive Sensing: Ins and Outs of Active Sensing application note (SNOA926).

8.3.2 The CAPDAC

The FDC1004Q full-scale input range is ±15 pF. The part can accept a higher capacitance on the input and the common-mode or offset (constant component) capacitance can be balanced by the programmable on-chip CAPDACs. The CAPDAC can be viewed as a negative capacitance connected internally to the CINn pin. The relation between the input capacitance and output data can be expressed as DATA = (CINn – CAPDAC), n = 1...4. The CAPDACs have a 5-bit resolution, monotonic transfer function, are well matched to each other, and have a defined temperature coefficient.

8.3.3 Capacitive System Offset Calibration

The capacitive offset can be due to many factors including the initial capacitance of the sensor, parasitic capacitances of board traces, and the capacitance of any other connections between the sensor and the FDC.

The parasitic capacitances of the FDC1004Q are calibrated out at production. If there are other sources of offset in the system, it may be necessary to calibrate the system capacitance offset in the application. Any offset in the capacitance input larger than ½ LSB of the CAPDAC should first be removed using the on-chip CAPDACs. Any residual offset of approximately 1 pF can then be removed by using the capacitance offset calibration register. The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the host controller and reloaded as part of the FDC1004Q setup.

8.3.4 Capacitive Gain Calibration

The gain is factory calibrated up to ±15 pF in the production for each part individually. The factory gain coefficient is stored in a one-time programmable (OTP) memory.

The gain can be temporarily changed by setting the Gain Calibration Register (registers 0x11 to 0x14) for the appropriate CINn pin, although the factory gain coefficient will be restored after power-up or reset.

The part is tested and specified for use only with the default factory calibration coefficient. Adjusting the Gain calibration can be used to normalize the capacitance measurement of the CINn input channels.

8.4.1 Single Ended Measurement

The FDC1004Q can be used for interfacing to a single-ended capacitive sensor. In this configuration the sensor should be connected to the input CINn (n = 1..4) pins of the FDC1004Q and GND. The capacitance-to-digital convertor (without using the CAPDAC, CAPDAC= 0pF) measures the positive (or the negative) input capacitance in the range of 0 pF to 15 pF. The CAPDAC can be used for programmable shifting of the input range. In this case it is possible to measure input capacitance in the range of 0 pF to ±15 pF which are on top of an offset capacitance up to 100 pF. In single ended measurements with CAPDAC disabled SHLD1 is internally shorted to SHLD2 (see Figure 10); if CAPDAC is enabled SHLD2 is floating (see Figure 11). The single ended mode is enabled when the CHB register of the Measurements configuration registers (see Table 4) are set to b100 or b111.

Figure 10. Single-Ended Configuration with CAPDAC Disabled

Figure 11. Single-Ended Configuration with CAPDAC Enabled

8.4.2 Differential Measurement

When the FDC1004Q is used for interfacing to a differential capacitive sensor, each of the two input capacitances must be less than 115 pF. In this configuration the CAPDAC is disabled. The absolute value of the difference between the two input capacitances should be kept below 15 pF to avoid introducing errors in the measurement. In differential measurements, SHLD1 is assigned to CHn and SHLD2 is assigned to CHm, where n < m. For instance in the measurement CIN1 – CIN2, where CHA = CIN1 and CHB = CIN2 (see Table 4), SHDL1 is assigned to CIN1 and SHDL2 is to CIN2. Differential sensors made with S1 versus S3 and S2 versus S4 are shown below in Figure 12. S1 and S2 are alternatively connected to CHA and the S3 and S4 are alternatively connected to CHB, the shield signals are connected as explained in previous paragraph. The FDC1004Q will perform a differential measurement when CHB field of the Measurements Configuration Registers (refer to Table 4) is less than to b100.

This configuration is very useful in applications where environment conditions need to be tracked. The differential measurement between the main electrode and the environment electrode makes the measurement independent of the environment conditions.

Figure 12. Differential Configuration

8.5.1 Serial Bus Address

To communicate with the FDC1004Q, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates the intent to execute a read or write operation. The seven bit address for the FDC1004Q is (MSB first): b101 0000.

8.5.2 Read/Write Operations

Access a particular register on the FDC1004Q by writing the appropriate value to the Pointer Register. The pointer value is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the FDC1004Q requires a value for the pointer register. When reading from the FDC1004Q, the last value stored in the pointer by a write operation is used to determine which register is read by a read operation. To change the pointer register for a read operation, a new value must be written to the pointer. This transaction is accomplished by issuing the slave address byte with the R/W bit low, followed by the pointer byte. No additional data is required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command. Note that register bytes are sent MSB first, followed by the LSB. A write operation in a read only registers such as MANUFACTURER ID or SERIAL ID returns a NACK after each data byte; read/write operation to unused address returns a NACK after the pointer; a read/write operation with incorrect I₂C address returns a NACK after the I²C address.

Figure 13. Write Frame

Figure 14. Read Frame

8.5.3 Device Usage

The basic usage model of the FDC1004Q is to simply follow these steps:

1. Configure measurements (for details, refer to Measurement Configuration).
2. Trigger a measurement set (for details, refer to Triggering Measurements).
3. Wait for measurement completion (for details, refer to Wait for Measurement Completion).
4. Read measurement data (for details, refer to Read of Measurement Result).

Table 1. Register Map

8.6.1 Registers

The FDC1004Q has an 8-bit pointer used to address a given data register. The pointer identifies which of the data registers should respond to a read or write command on the two-wire bus. This register is set with every write command. A write command must be issued to set the proper value in the pointer before executing a read command. The power-on reset (POR) value of the pointer is 0x00.

Table 2. Measurement Registers Description (0x00, 0x02, 0x04, 0x06)

Table 3. Measurement Registers Description (0x01, 0x03, 0x05, 0x07)

8.6.2 Measurement Configuration Registers

These registers configure the input channels and CAPDAC setting for a measurement.

8.6.3 FDC Configuration Register

This register configures measurement triggering and reports measurement completion.

8.6.4 Offset Calibration Registers

These registers configure a digitized capacitance value in the range of -16 pF to 16 pF (max residual offset 250 aF) that can be added to each channel in order to remove parasitic capacitance due to external circuitry. In addition to the offset calibration capacitance which is a fine-tune offset capacitance, it is possible to support a larger offset by using the CAPDAC (for up to 100 pF). These 16-bit registers are formatted as a fixed point number, where the first 5 bits represents the integer portion of the capacitance in Two’s complement format, and the remaining 11 bits represent the fractional portion of the capacitance.

8.6.5 Gain Calibration Registers

These registers contain a gain factor correction in the range of 0 to 4 that can be applied to each channel in order to remove gain mismatch due to the external circuitry. This 16-bit register is formatted as a fixed point number, where the 2 MSBs of the GAIN_CALn register correspond to an integer portion of the gain correction, and the remaining 14 bits represent the fractional portion of the gain correction. The result of the conversion represents a number without dimensions.

The Gain can be set according to the following formula:

Gain = GAIN_CAL[15:0]/2¹⁴

8.6.6 Manufacturer ID Register

This register contains a factory-programmable identification value that identifies this device as being manufactured by Texas Instruments. This register distinguishes this device from other devices that are on the same I²C bus. The manufacturer ID reads 0x5449.

8.6.7 Device ID Register

This register contains a factory-programmable identification value that identifies this device as a FDC1004Q. This register distinguishes this device from other devices that are on the same I2C bus. The Device ID for the FDC1004Q is 0x1004.