ZHCSDR2A April   2015  – October 2024 FDC1004-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Voltage Level
    7. 5.7 I2C Interface Timing
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 The Shield
      2. 6.3.2 The CAPDAC
      3. 6.3.3 Capacitive System Offset Calibration
      4. 6.3.4 Capacitive Gain Calibration
    4. 6.4 Device Functional Modes
      1. 6.4.1 Single Ended Measurement
      2. 6.4.2 Differential Measurement
    5. 6.5 Programming
      1. 6.5.1 Serial Bus Address
      2. 6.5.2 Read/Write Operations
      3. 6.5.3 Device Usage
        1. 6.5.3.1 Measurement Configuration
        2. 6.5.3.2 Triggering Measurements
        3. 6.5.3.3 Wait for Measurement Completion
        4. 6.5.3.4 Read of Measurement Result
    6. 6.6 Register Maps
      1. 6.6.1 Registers
        1. 6.6.1.1 Capacitive Measurement Registers
      2. 6.6.2 Measurement Registers
      3. 6.6.3 Measurement Configuration Registers
      4. 6.6.4 FDC Configuration Register
      5. 6.6.5 Offset Calibration Registers
      6. 6.6.6 Gain Calibration Registers
      7. 6.6.7 Manufacturer ID Register
      8. 6.6.8 Device ID Register
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Liquid Level Sensor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Initialization Set Up
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Pin Configuration and Functions

FDC1004-Q1 DGS Package10 Pin VSSOPTop ViewFigure 4-1 DGS Package10 Pin VSSOPTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
SHLD1 1 A Capacitive Input Active AC Shielding.
CIN1 2 A Capacitive Input. The measured capacitance is connected between the CIN1 pin and GND. If not used, leave this pin as an open circuit.
CIN2 3 A Capacitive Input. The measured capacitance is connected between the CIN2 pin and GND. If not used, leave this pin as an open circuit.
CIN3 4 A Capacitive Input. The measured capacitance is connected between the CIN3 pin and GND. If not used, leave this pin as an open circuit.
CIN4 5 A Capacitive Input. The measured capacitance is connected between the CIN4 pin and GND. If not used, leave this pin as an open circuit.
SHLD2 6 A Capacitive Input Active AC Shielding.
GND 7 G Ground
VDD 8 P Power Supply Voltage. Decouple this pin to GND, using a low impedance capacitor, for example in combination with a 1μF tantalum and a 0.1μF multilayer ceramic.
SCL 9 I Serial Interface Clock Input. Connects to the controller clock line. Requires pullup resistor if not already provided elsewhere in the system.
SDA 10 I/O Serial Interface Bidirectional Data. Connects to the controller data line. Requires a pullup resistor if not provided elsewhere in the system.
(1) P=Power, G=Ground, I=Input, O=Output, A=Analog, I/O=Bidirectional Input/Output
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