ZHCSDR2A April   2015  – October 2024 FDC1004-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Voltage Level
    7. 5.7 I2C Interface Timing
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 The Shield
      2. 6.3.2 The CAPDAC
      3. 6.3.3 Capacitive System Offset Calibration
      4. 6.3.4 Capacitive Gain Calibration
    4. 6.4 Device Functional Modes
      1. 6.4.1 Single Ended Measurement
      2. 6.4.2 Differential Measurement
    5. 6.5 Programming
      1. 6.5.1 Serial Bus Address
      2. 6.5.2 Read/Write Operations
      3. 6.5.3 Device Usage
        1. 6.5.3.1 Measurement Configuration
        2. 6.5.3.2 Triggering Measurements
        3. 6.5.3.3 Wait for Measurement Completion
        4. 6.5.3.4 Read of Measurement Result
    6. 6.6 Register Maps
      1. 6.6.1 Registers
        1. 6.6.1.1 Capacitive Measurement Registers
      2. 6.6.2 Measurement Registers
      3. 6.6.3 Measurement Configuration Registers
      4. 6.6.4 FDC Configuration Register
      5. 6.6.5 Offset Calibration Registers
      6. 6.6.6 Gain Calibration Registers
      7. 6.6.7 Manufacturer ID Register
      8. 6.6.8 Device ID Register
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Liquid Level Sensor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Initialization Set Up
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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6.6.3 Measurement Configuration Registers

These registers configure the input channels and CAPDAC setting for a measurement.

Table 6-4 Measurement Configuration Registers Description (0x08, 0x09, 0x0A, 0x0B)
Field NameBitsDescription
CHA(1)(2)[15:13]Positive input channel capacitive to digital converterb000CIN1
b001CIN2
b010CIN3
b011CIN4
CHB(1)(2)[12:10]Negative input channel capacitive to digital converterb000CIN1
b001CIN2
b010CIN3
b011CIN4
b100CAPDAC
b111DISABLED
CAPDAC[9:5]Offset Capacitanceb000000pF (minimum programmable offset)
- - - - -Configure the single-ended measurement capacitive offset:
Coffset = CAPDAC x 3.125pF
b1111196.875pF (maximum programmable offset)
RESERVED[04:00]ReservedReserved, always 0 (read only)
(1) It is not permitted to configure a measurement where the CHA field and CHB field hold the same value (for example, if CHA=b010, CHB cannot also be set to b010).
(2) It is not permitted to configure a differential measurement between CHA and CHB where CHA > CHB (for example, if CHA= b010, CHB cannot be b001 or b000).
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