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ZHCSDR2A April 2015 – October 2024 FDC1004-Q1

PRODUCTION DATA

5.7 I²C Interface Timing

Over recommended operating free-air temperature range, V_DD = 3.3V, for T_A = T_J = 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_SCL	Clock frequency⁽¹⁾		10	400	kHz
t_LOW	Clock low time⁽¹⁾		1.3		µs
t_HIGH	Clock high time⁽¹⁾		0.6		µs
t_HD;STA	Hold time (repeated) START condition⁽¹⁾	After this period, the first clock pulse is generated	0.6		µs
t_SU;STA	Set-up time for a repeated START condition⁽¹⁾		0.6		µs
t_HD;DAT	Data hold time⁽¹⁾⁽²⁾		0		ns
t_SU;DAT	Data setup time⁽¹⁾		100		ns
t_f	SDA fall time⁽¹⁾	IL ≤ 3mA; CL ≤ 400pF		300	ns
t_SU;STO	Set-up time for STOP condition⁽¹⁾		0.6		µs
t_BUF	Bus free time between a STOP and START condition⁽¹⁾		1.3		µs
t_VD;DAT	Data valid time⁽¹⁾			0.9	ns
t_VD;ACK	Data valid acknowledge time⁽¹⁾			0.9	ns
t_SP	Pulse width of spikes that must be suppressed by the input filter⁽¹⁾			50	ns

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) The FDC1004-Q1 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.

Figure 5-1 I²C Timing