ZHCSF09 May   2016 FDC2112-Q1 , FDC2114-Q1 , FDC2212-Q1 , FDC2214-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics - I2C
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Clocking Architecture
      2. 7.3.2 Multi-Channel and Single-Channel Operation
        1. 7.3.2.1 Gain and Offset (FDC2112, FDC2114 only)
      3. 7.3.3 Current Drive Control Registers
      4. 7.3.4 Device Status Registers
      5. 7.3.5 Input Deglitch Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Normal (Conversion) Mode
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Shutdown Mode
        1. 7.4.4.1 Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Specifications
    6. 7.6 Register Maps
      1. 7.6.1  Register List
      2. 7.6.2  Address 0x00, DATA_CH0
      3. 7.6.3  Address 0x01, DATA_LSB_CH0 (FDC2212 / FDC2214 only)
      4. 7.6.4  Address 0x02, DATA_CH1
      5. 7.6.5  Address 0x03, DATA_LSB_CH1 (FDC2212 / FDC2214 only)
      6. 7.6.6  Address 0x04, DATA_CH2 (FDC2114, FDC2214 only)
      7. 7.6.7  Address 0x05, DATA_LSB_CH2 (FDC2214 only)
      8. 7.6.8  Address 0x06, DATA_CH3 (FDC2114, FDC2214 only)
      9. 7.6.9  Address 0x07, DATA_LSB_CH3 (FDC2214 only)
      10. 7.6.10 Address 0x08, RCOUNT_CH0
      11. 7.6.11 Address 0x09, RCOUNT_CH1
      12. 7.6.12 Address 0x0A, RCOUNT_CH2 (FDC2114, FDC2214 only)
      13. 7.6.13 Address 0x0B, RCOUNT_CH3 (FDC2114, FDC2214 only)
      14. 7.6.14 Address 0x0C, OFFSET_CH0 (FDC21112 / FDC2114 only)
      15. 7.6.15 Address 0x0D, OFFSET_CH1 (FDC21112 / FDC2114 only)
      16. 7.6.16 Address 0x0E, OFFSET_CH2 (FDC2114 only)
      17. 7.6.17 Address 0x0F, OFFSET_CH3 (FDC2114 only)
      18. 7.6.18 Address 0x10, SETTLECOUNT_CH0
      19. 7.6.19 Address 0x11, SETTLECOUNT_CH1
      20. 7.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114, FDC2214 only)
      21. 7.6.21 Address 0x13, SETTLECOUNT_CH3 (FDC2114, FDC2214 only)
      22. 7.6.22 Address 0x14, CLOCK_DIVIDERS_CH0
      23. 7.6.23 Address 0x15, CLOCK_DIVIDERS_CH1
      24. 7.6.24 Address 0x16, CLOCK_DIVIDERS_CH2 (FDC2114, FDC2214 only)
      25. 7.6.25 Address 0x17, CLOCK_DIVIDERS_CH3 (FDC2114, FDC2214 only)
      26. 7.6.26 Address 0x18, STATUS
      27. 7.6.27 Address 0x19, ERROR_CONFIG
      28. 7.6.28 Address 0x1A, CONFIG
      29. 7.6.29 Address 0x1B, MUX_CONFIG
      30. 7.6.30 Address 0x1C, RESET_DEV
      31. 7.6.31 Address 0x1E, DRIVE_CURRENT_CH0
      32. 7.6.32 Address 0x1F, DRIVE_CURRENT_CH1
      33. 7.6.33 Address 0x20, DRIVE_CURRENT_CH2 (FDC2114 / FDC2214 only)
      34. 7.6.34 Address 0x21, DRIVE_CURRENT_CH3 (FDC2114 / FDC2214 only)
      35. 7.6.35 Address 0x7E, MANUFACTURER_ID
      36. 7.6.36 Address 0x7F, DEVICE_ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sensor Configuration
      2. 8.1.2 Shield
      3. 8.1.3 Power-Cycled Applications
      4. 8.1.4 Inductor Self-Resonant Frequency
      5. 8.1.5 Application Curves for Proximity Sensing
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Recommended Initial Register Configuration Values
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 相关链接
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Detailed Description

7.1 Overview

The FDC2112, FDC2114, FDC2212, and FDC2214 are high-resolution, multichannel capacitance-to-digital converters for implementing capacitive sensing solutions. In contrast to traditional switched-capacitance architectures, the FDC2112, FDC2114, FDC2212, and FDC2214 employ an L-C resonator, also known as L-C tank, as a sensor. The narrow-band architecture allows unprecedented EMI immunity and greatly reduced noise floor when compared to other capacitive sensing solutions.

Using this approach, a change in capacitance of the L-C tank can be observed as a shift in the resonant frequency. Using this principle, the FDC is a capacitance-to-digital converter (FDC) that measures the oscillation frequency of an LC resonator. The device outputs a digital value that is proportional to frequency. This frequency measurement can be converted to an equivalent capacitance

7.2 Functional Block Diagrams

FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 2_channel_block_snoscz5.gif Figure 10. Block Diagram for the FDC2112 and FDC2212
FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 4_channel_block_snoscz5.gif Figure 11. Block Diagram for the FDC2114 and FDC2214

The FDC is composed of front-end resonant circuit drivers, followed by a multiplexer that sequences through the active channels, connecting them to the core that measures and digitizes the sensor frequency (fSENSOR). The core uses a reference frequency (fREF) to measure the sensor frequency. fREF is derived from either an internal reference clock (oscillator), or an externally supplied clock. The digitized output for each channel is proportional to the ratio of fSENSOR/fREF. The I2C interface is used to support device configuration and to transmit the digitized frequency values to a host processor. The FDC can be placed in shutdown mode, saving current, using the SD pin. The INTB pin may be configured to notify the host of changes in system status.

7.3 Feature Description

7.3.1 Clocking Architecture

Figure 12 shows the clock dividers and multiplexers of the FDC.

FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 clocking_snoscz5.gif
1. FDC2114 / FDC2214 only
Figure 12. Clocking Diagram

In Figure 12, the key clocks are fIN, fREF, and fCLK. fCLK is selected from either the internal clock source or external clock source (CLKIN). The frequency measurement reference clock, fREF, is derived from the fCLK source. TI recommends that precision applications use an external master clock that offers the stability and accuracy requirements needed for the application. The internal oscillator may be used in applications that require low cost and do not require high precision. The fINx clock is derived from sensor frequency for a channel x, fSENSORx. fREFx and fINx must meet the requirements listed in Table 1, depending on whether fCLK (master clock) is the internal or external clock.

Table 1. Clock Configuration Requirements

MODE(1) CLKIN SOURCE VALID fREFx RANGE (MHz) VALID fINx RANGE SET CHx_FIN_SEL to (2) SET CHx_SETTLECOUNT to SET CHx_RCOUNT to
Multi-channel Internal fREFx ≤ 55 < fREFx /4 Differential sensor configuration:
b01: 0.01MHz to 8.75MHz (divide by 1)
b10: 5MHz to 10MHz (divide by 2)
Single-ended sensor configuration
b10: 0.01MHz to 10MHz (divide by 2)		 > 3 > 8
External fREFx ≤ 40
Single-channel Either external or internal fREFx ≤ 35
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.
(2) Refer to Sensor Configuration for information on differential and single-ended sensor configurations.

Table 2 shows the clock configuration registers for all channels.

Table 2. Clock Configuration Registers

CHANNEL(1) CLOCK REGISTER FIELD [ BIT(S) ] VALUE
All fCLK = Master Clock Source CONFIG, addr 0x1A REF_CLK_SRC [9] b0 = internal oscillator is used as the master clock
b1 = external clock source is used as the master clock
0 fREF0 CLOCK_DIVIDERS_CH0, addr 0x14 CH0_FREF_DIVIDER [9:0] fREF0 = fCLK / CH0_FREF_DIVIDER
1 fREF1 CLOCK_DIVIDERS_CH1, addr 0x15 CH1_FREF_DIVIDER [9:0] fREF1 = fCLK / CH1_FREF_DIVIDER
2 fREF2 CLOCK_DIVIDERS_CH2, addr 0x16 CH2_FREF_DIVIDER [9:0] fREF2 = fCLK / CH2_FREF_DIVIDER
3 fREF3 CLOCK_DIVIDERS_CH3, addr 0x17 CH3_FREF_DIVIDER [9:0] fREF3 = fCLK / CH3_FREF_DIVIDER
0 fIN0 CLOCK_DIVIDERS_CH0, addr 0x14 CH0_FIN_SEL [13:12] fIN0 = fSENSOR0 / CH0_FIN_SEL
1 fIN1 CLOCK_DIVIDERS_CH1, addr 0x15 CH1_FIN_SEL [13:12] fIN1 = fSENSOR1 / CH1_FIN_SEL
2 fIN2 CLOCK_DIVIDERS_CH2, addr 0x16 CH2_FIN_SEL [13:12] fIN2 = fSENSOR2 / CH2_FIN_SEL
3 fIN3 CLOCK_DIVIDERS_CH3, addr 0x17 CH3_FIN_SEL [13:12] fIN3 = fSENSOR3 / CH3_FIN_SEL
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214

7.3.2 Multi-Channel and Single-Channel Operation

The multi-channel package of the FDC enables the user to save board space and support flexible system design. For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant frequency of the sensor. Using a second sensor as a reference provides the capability to cancel out a temperature shift. When operated in multi-channel mode, the FDC sequentially samples the active channels. In single-channel mode, the FDC samples a single channel, which is selectable. Table 3 shows the registers and values that are used to configure either multi-channel or single-channel modes.

Table 3. Single- and Multi-Channel Configuration Registers

MODE REGISTER FIELD [ BIT(S) ] VALUE
Single channel CONFIG, addr 0x1A ACTIVE_CHAN [15:14] 00 = chan 0
01 = chan 1
10 = chan 2
11 = chan 3
MUX_CONFIG addr 0x1B AUTOSCAN_EN [15] 0 = continuous conversion on a single channel (default)
Multi-channel MUX_CONFIG addr 0x1B AUTOSCAN_EN [15] 1 = continuous conversion on multiple channels
MUX_CONFIG addr 0x1B RR_SEQUENCE [14:13] 00 = Ch0, Ch 1
01 = Ch0, Ch 1, Ch 2
10 = Ch0, CH1, Ch2, Ch3

The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the reference frequency.

The data output (DATAx) of the FDC2112 and FDC2114 is expressed as the 12 MSBs of a 16-bit result:

Equation 1. FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 eq22_snoscz5.gif

The data output (DATAx) of the FDC2212 and FDC2214 is expressed as:

Equation 2. FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 eq23_snoscz5.gif

Table 4 lists the registers that contain the fixed point sample values for each channel.

Table 4. Sample Data Registers

CHANNEL(2) REGISTER(1) FIELD NAME [ BITS(S) ] AND VALUE (FDC2112, FDC2114) FIELD NAME [ BITS(S) ] AND VALUE (FDC2212, FDC2214) (3)(4)
0 DATA_CH0, addr 0x00 DATA0 [11:0]:
12 bits of the 16 bit conversion result.
0x000 = under range
0xfff = over range		 DATA0 [27:16]:
12 MSBs of the 28 bit conversion result
DATA_LSB_CH0, addr 0x01 Not applicable DATA0 [15:0]:
16 LSBs of the 28 bit conversion result
1 DATA_CH1, addr 0x02 DATA1 [11:0]:
12 bits of the 16 bit conversion result.
0x000 = under range
0xfff = over range		 DATA1 [27:16]:
12 MSBs of the 28 bit conversion result
DATA_LSB_CH1, addr 0x03 Not applicable DATA1 [15:0]:
16 LSBs of the 28 bit conversion result
2 DATA_CH2, addr 0x04 DATA2 [11:0]:
12 bits of the 16 bit conversion result.
0x000 = under range
0xfff = over range		 DATA2 [27:16]:
12 MSBs of the 28 bit conversion result
DATA_LSB_CH2, addr 0x05 Not applicable DATA2 [15:0]:
16 LSBs of the 28 bit conversion result
3 DATA_CH3, addr 0x06 DATA3 [11:0]:
12 bits of the 16 bit conversion result.
0x000 = under range
0xfff = over range		 DATA3 [27:16]:
12 MSBs of the 28 bit conversion result
DATA_LSB_CH3, addr 0x07 Not applicable DATA3 [15:0]:
16 LSBs of the 28 bit conversion result
(1) The DATA_CHx.DATAx register must always be read first, followed by the DATA_LSB_ CHx.DATAx register of the same channel to ensure data coherency.
(2) Channels 2 and 3 are only available for FDC2114 and FDC2214.
(3) A DATA value of 0x0000000 = under range for FDC2212/FDC2214.
(4) A DATA value of 0xFFFFFFF = over range for FDC2212/FDC2214.

When the FDC sequences through the channels in multi-channel mode, the dwell time interval for each channel is the sum of three parts:

  1. sensor activation time
  2. conversion time
  3. channel switch delay

The sensor activation time is the amount of settling time required for the sensor oscillation to stabilize, as shown in Figure 13. The settling wait time is programmable and should be set to a value that is long enough to allow stable oscillation. The settling wait time for channel x is given by:

Equation 3. tSx = (CHX_SETTLECOUNTˣ16)/fREFx

Table 5 illustrates the registers and values for configuring the settling time for each channel.

FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 sequential_mode_ch_seq_snoscy9.gif Figure 13. Multi-channel Mode Sequencing
FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 single_ch_conv_mode_snoscy9.gif Figure 14. Single-channel Mode Sequencing

Table 5. Settling Time Register Configuration

CHANNEL(1) REGISTER FIELD CONVERSION TIME(2)
0 SETTLECOUNT_CH0, addr 0x10 CH0_SETTLECOUNT [15:0] (CH0_SETTLECOUNT*16)/fREF0
1 SETTLECOUNT_CH1, addr 0x11 CH1_SETTLECOUNT [15:0] (CH1_SETTLECOUNT*16)/fREF1
2 SETTLECOUNT_CH2, addr 0x12 CH2_SETTLECOUNT [15:0] (CH2_SETTLECOUNT*16)/fREF2
3 SETTLECOUNT_CH3, addr 0x13 CH3_SETTLECOUNT [15:0] (CH3_SETTLECOUNT*16)/fREF3
(1) Channels 2 and 3 are available only in the FDC2114 and FDC2214.
(2) fREFx is the reference frequency configured for the channel.

The SETTLECOUNT for any channel x must satisfy:

    Equation 4. CHx_SETTLECOUNT > Vpk × fREFx × C × π2 / (32 × IDRIVEX)

    where

    • Vpk = Peak oscillation amplitude at the programmed IDRIVE setting
    • fREFx = Reference frequency for Channel x
    • C = sensor capacitance including parasitic PCB capacitance
    • IDRIVEX = setting programmed into the IDRIVE register in amps

    Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08, program the register to 7 or higher).

    The conversion time represents the number of reference clock cycles used to measure the sensor frequency. It is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:

    Equation 5. tCx = (CHx_RCOUNT × 16 + 4) /fREFx

    The reference count value must be chosen to support the required number of effective bits (ENOB). For example, if an ENOB of 13 bits is required, then a minimum conversion time of 213 = 8192 clock cycles is required. 8192 clock cycles correspond to a CHx_RCOUNT value of 0x0200.

Table 6. Conversion Time Configuration Registers, Channels 0 - 3(1)

CHANNEL REGISTER FIELD [ BIT(S) ] CONVERSION TIME
0 RCOUNT_CH0, addr 0x08 CH0_RCOUNT [15:0] (CH0_RCOUNT × 16)/fREF0
1 RCOUNT_CH1, addr 0x09 CH1_RCOUNT [15:0] (CH1_RCOUNT × 16)/fREF1
2 RCOUNT_CH2, addr 0x0A CH2_RCOUNT [15:0] (CH2_RCOUNT × 16)/fREF2
3 RCOUNT_CH3, addr 0x0B CH3_RCOUNT [15:0] (CH3_RCOUNT × 16)/fREF3
(1) Channels 2 and 3 are available only for FDC2114 and FDC2214.

The typical channel switch delay time between the end of conversion and the beginning of sensor activation of the subsequent channel is:

Equation 6. Channel Switch Delay = 692 ns + 5 / fref

The deterministic conversion time of the FDC allows data polling at a fixed interval. For example, if the programmed SETTLECOUNT is 128 FREF cycles (SETTLECOUNT = 0x0008) and RCOUNT is 512 FREF cycles (RCOUNT=0x0020), then one conversion takes 3.2 ms (sensor-activation time) + 12.8ms (conversion time) + 0.8µs (channel-switch delay) = 16.0 ms per channel. If the FDC is configured for dual-channel operation by setting AUTOSCAN_EN = 1 and RR_SEQUENCE = 00, then one full set of conversion results will be available from the data registers every 32 ms.

A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register description in Register Maps).

7.3.2.1 Gain and Offset (FDC2112, FDC2114 only)

The FDC2112 and FDC2114 have internal 16-bit data converters, but the standard conversion output word width is only 12 bits; therefore only 12 of the 16 bits are available from the data registers. By default, the gain feature is disabled and the DATA registers contain the 12 MSBs of the 16-bit word. However, it is possible to shift the data output by up to 4 bits. Figure 15 shows the segment of the 16-bit sample that is reported for each possible gain setting.

FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 conversion_data_output_gain_snoscy9.gif Figure 15. Conversion Data Output Gain

For systems in which the sensor signal variation is less than 25% of the full-scale range, the FDC can report conversion results with higher resolution by setting the output gain. the output gain is applied to all device channels. An output gain can be used to apply a 2-bit, 3-bit, or 4-bit shift to the output code for all channels, allowing access to the 4 LSBs of the original 16-bit result. The MSBs of the sample are shifted out when a gain is applied. Do not use the output gain if the MSBs of any active channel are toggling, as the MSBs for that channel will be lost when gain is applied.

Example: If the conversion result for a channel is 0x07A3, with OUTPUT_GAIN = 0x0, the reported output code is 0x07A. If OUTPUT_GAIN is set to 0x3 in the same condition, then the reported output code is 0x7A3. The original 4 MSBs (0x0) are no longer accessible.

Table 7. Output Gain Register (FDC2112 and FDC2114 only)

CHANNEL(1) REGISTER FIELD [ BIT(S) ] VALUES EFFECTIVE RESOLUTION (BITS) OUTPUT RANGE
All RESET_DEV, addr 0x1C OUTPUT_GAIN [ 10:9 ] 00 (default): Gain =1 (0 bits shift) 12 100% full scale
01: Gain = 4 (2 bits left shift) 14 25% full scale
10: Gain = 8 (3 bits left shift) 15 12.5% full scale
11 : Gain = 16 (4 bits left shift) 16 6.25% full scale
(1) Channels 2 and 3 are available for FDC2114 only.

An offset value may be subtracted from each DATA value to compensate for a frequency offset or maximize the dynamic range of the sample data. The offset values should be < fSENSORx_MIN / fREFx. Otherwise, the offset might be so large that it masks the LSBs which are changing.

Table 8. Frequency Offset Registers

CHANNEL(1) REGISTER FIELD [ BIT(S) ] VALUE
0 OFFSET_CH0, addr 0x0C CH0_OFFSET [ 15:0 ] fOFFSET0 = CH0_OFFSET × (fREF0/216)
1 OFFSET_CH1, addr 0x0D CH1_OFFSET [ 15:0 ] fOFFSET1 = CH1_OFFSET × (fREF1/216)
2 OFFSET_CH2, addr 0x0E CH2_OFFSET [ 15:0 ] fOFFSET2 = CH2_OFFSET × (fREF2/216)
3 OFFSET_CH3, addr 0x0F CH3_OFFSET [ 15:0 ] fOFFSET3 = CH3_OFFSET × (fREF3/216)
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.

The sensor capacitance CSENSE of a differential sensor configuration can be determined by:

Equation 7. FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 eq24_snoscz5.gif

where

  • C = parallel sensor capacitance (see Figure 55)

The FDC2112 and FDC2114 sensor frequency fSENSORx can be determined by:

Equation 8. FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 eq25_snoscz5.gif

where

  • DATAx = Conversion result from the DATA_CHx register
  • CHx_OFFSET = Offset value set in the OFFSET_CHx register
  • OUTPUT_GAIN = output multiplication factor set in the RESET_DEVICE.OUTPUT_GAIN register

The FDC2212 and FDC2214 sensor frequency fSENSORx can be determined by:

Equation 9. FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 eq26_snoscz5.gif (FDC2212, FDC2214)

where

  • DATAx = Conversion result from the DATA_CHx register

7.3.3 Current Drive Control Registers

The registers listed in Table 9 are used to control the sensor drive current. The recommendations listed in the last column of the table should be followed.

Table 9. Current Drive Control Registers

CHANNEL(1) REGISTER FIELD [ BIT(S) ] VALUE
All CONFIG, addr 0x1A SENSOR_ACTIVATE_SEL [11] Sets current drive for sensor activation. Recommended value is b0 (full current mode).
0 CONFIG, addr 0x1A HIGH_CURRENT_DRV [6] b0 = normal current drive (1.5 mA)
b1 = Increased current drive (> 1.5 mA) for Ch 0 in single channel mode only. Cannot be used in multi-channel mode.
0 DRIVE_CURRENT_CH0, addr 0x1E CH0_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 0. Set such that 1.2 V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
1 DRIVE_CURRENT_CH1, addr 0x1F CH1_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 1. Set such that 1.2 V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
2 DRIVE_CURRENT_CH2, addr 0x20 CH2_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 2. Set such that 1.2 V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
3 DRIVE_CURRENT_CH3, addr 0x21 CH3_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 3 . Set such that 1.2 V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
(1) Channels 2 and 3 are available for FDC2114 and FDC2214 only.

The CHx_IDRIVE field should be programmed such that the sensor oscillates at an amplitude between 1.2 Vpk (VSENSORMIN) and 1.8 Vpk (VSENSORMAX). An IDRIVE value of 00000 corresponds to 16 µA, and IDRIVE = b11111 corresponds to 1563 µA.

A high sensor current drive mode can be enabled to drive sensor coils with > 1.5mA on channel 0, only in single channel mode. This feature can be used when the sensor minimum recommended oscillation amplitude of 1.2V cannot be achieved with the highest IDRIVE setting. Set the HIGH_CURRENT_DRV register bit to b1 to enable this mode.

7.3.4 Device Status Registers

The registers listed in Table 10 may be used to read device status.

Table 10. Status Registers

CHANNEL(1) REGISTER FIELDS [ BIT(S) ] VALUES
All STATUS, addr 0x18 12 fields are available that contain various status bits [ 15:0 ] Refer to Register Maps for a description of the individual status bits.
All STATUS_CONFIG, addr 0x19 12 fields are available that are used to configure status reporting [ 15:0 ] Refer to Register Maps for a description of the individual error configuration bits.
(1) Channels 2 and 3 are available for FDC2114 and FDC2114 only.

See the STATUS and STATUS_CONFIG register description in Register Maps. These registers can be configured to trigger an interrupt on the INTB pin for certain events. The following conditions must be met:

  1. The error or status register must be unmasked by enabling the appropriate register bit in the STATUS_CONFIG register
  2. The INTB function must be enabled by setting CONFIG.INTB_DIS to 0

When a bit field in the STATUS register is set, the entire STATUS register content is held until read or until the DATA_CHx register is read. Reading also de-asserts INTB.

Interrupts are cleared by one of the following events:

  1. Entering sleep mode
  2. Power-on reset (POR)
  3. Device enters shutdown mode (SD is asserted)
  4. S/W reset
  5. I2C read of the STATUS register: Reading the STATUS register clears any error status bit set in STATUS along with the ERR_CHAN field and de-assert INTB

Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.

7.3.5 Input Deglitch Filter

The input deglitch filter suppresses EMI and ringing above the sensor frequency. It does not impact the conversion result as long as its bandwidth is configured to be above the maximum sensor frequency. The input deglitch filter can be configured in MUX_CONFIG.DEGLITCH register field as shown in Table 11. For optimal performance, TI recommends selection of the lowest setting that exceeds the sensor oscillation frequency. For example, if the maximum sensor frequency is 2 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz).

Table 11. Input Deglitch Filter Register

CHANNEL(1) MUX_CONFIG.DEGLITCH (addr 0x1B) REGISTER VALUE DEGLITCH FREQUENCY
ALL 001 1 MHz
ALL 100 3.3 MHz
ALL 101 10 MHz
ALL 011 33 MHz
(1) Channels 2 and 3 are available for FDC2114 / FDC2214 only.

7.4 Device Functional Modes

7.4.1 Start-Up Mode

When the FDC powers up, it enters into sleep mode and waits for configuration. Once the device is configured, exit sleep mode by setting CONFIG.SLEEP_MODE_EN to b0.

TI recommends configuring the FDC while in sleep mode. If a setting on the FDC needs to be changed, return the device to sleep mode, change the appropriate register, and then exit sleep mode.

7.4.2 Normal (Conversion) Mode

When operating in the normal (conversion) mode, the FDC is periodically sampling the frequency of the sensor(s) and generating sample outputs for the active channel(s).

7.4.3 Sleep Mode

Sleep mode is entered by setting the CONFIG.SLEEP_MODE_EN register field to 1. While in this mode, the device configuration is maintained. To exit sleep mode, set the CONFIG.SLEEP_MODE_EN register field to 0. After setting CONFIG.SLEEP_MODE_EN to b0, sensor activation for the first conversion begins after 16,384 fINT clock cycles. While in sleep mode the I2C interface is functional so that register reads and writes can be performed. While in sleep mode, no conversions are performed. In addition, entering sleep mode will clear conversion results, any error condition, and de-assert the INTB pin.

7.4.4 Shutdown Mode

When the SD pin is set to high, the FDC enters shutdown mode. Shutdown mode is the lowest power state. To exit shutdown mode, set the SD pin to low. Entering shutdown mode returns all registers to their default state.

While in shutdown mode, no conversions are performed. In addition, entering shutdown mode clears any error condition and de-assert the INTB pin. While the device is in shutdown mode, is not possible to read to or write from the device via the I2C interface.

7.4.4.1 Reset

The FDC can be reset by writing to RESET_DEV.RESET_DEV. Any active conversion stops, and all register values return to their default value. This register bit always returns 0b when read.

7.5 Programming

The FDC device uses an I2C interface to access control and data registers.

7.5.1 I2C Interface Specifications

The FDC uses an extended start sequence with I2C for register access. The maximum speed of the I2C interface is 400 kbit/s. This sequence follows the standard I2C 7-bit slave address followed by an 8-bit pointer register byte to set the register address. When the ADDR pin is set low, the FDC I2C address is 0x2A; when the ADDR pin is set high, the FDC I2C address is 0x2B. The ADDR pin must not change state after the FDC exits Shutdown Mode.

FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 td_I2C_write_reg_seq_snoscy9.gif Figure 16. I2C Write Register Sequence
FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1 td_I2C_read_reg_seq_snoscy9.gif Figure 17. I2C Read Register Sequence

7.6 Register Maps

7.6.1 Register List

Fields indicated with Reserved must be written only with indicated values, otherwise improper device operation may occur. The R/W column indicates the Read-Write status of the corresponding field. A ‘R/W’ entry indicates read and write capability, a ‘R’ indicates read-only, and a ‘W’ indicates write-only.

Figure 18. Register List
ADDRESS NAME DEFAULT VALUE DESCRIPTION
0x00 DATA_CH0 0x0000 Channel 0 Conversion Result and status (FDC2112 / FDC2114 only)
0x0000 Channel 0 MSB Conversion Result and status (FDC2212 / FDC2214 only)
0x01 DATA_LSB_CH0 0x0000 Channel 0 LSB Conversion Result. Must be read after Register address 0x00 (FDC2212 / FDC2214 only)
0x02 DATA_CH1 0x0000 Channel 1 Conversion Result and status (FDC2112 / FDC2114 only)
0x0000 Channel 1 MSB Conversion Result and status (FDC2212 / FDC2214 only)
0x03 DATA_LSB_CH1 0x0000 Channel 1 LSB Conversion Result. Must be read after Register address 0x02 (FDC2212 / FDC2214 only)
0x04 DATA_CH2 0x0000 Channel 2 Conversion Result and status (FDC2114 only)
0x0000 Channel 2 MSB Conversion Result and status (FDC2214 only)
0x05 DATA_LSB_CH2 0x0000 Channel 2 LSB Conversion Result. Must be read after Register address 0x04 (FDC2214 only)
0x06 DATA_CH3 0x0000 Channel 3 Conversion Result and status (FDC2114 only)
0x0000 Channel 3 MSB Conversion Result and status (FDC2214 only)
0x07 DATA_LSB_CH3 0x0000 Channel 3 LSB Conversion Result. Must be read after Register address 0x06 (FDC2214 only)
0x08 RCOUNT_CH0 0x0080 Reference Count setting for Channel 0
0x09 RCOUNT_CH1 0x0080 Reference Count setting for Channel 1
0x0A RCOUNT_CH2 0x0080 Reference Count setting for Channel 2 (FDC2114 / FDC2214 only)
0x0B RCOUNT_CH3 0x0080 Reference Count setting for Channel 3 (FDC2114 / FDC2214 only)
0x0C OFFSET_CH0 0x0000 Offset value for Channel 0 (FDC2112 / FDC2114 only)
0x0D OFFSET_CH1 0x0000 Offset value for Channel 1 (FDC2112 / FDC2114 only)
0x0E OFFSET_CH2 0x0000 Offset value for Channel 2 (FDC2114 only)
0x0F OFFSET_CH3 0x0000 Offset value for Channel 3 (FDC2114 only)
0x10 SETTLECOUNT_CH0 0x0000 Channel 0 Settling Reference Count
0x11 SETTLECOUNT_CH1 0x0000 Channel 1 Settling Reference Count
0x12 SETTLECOUNT_CH2 0x0000 Channel 2 Settling Reference Count (FDC2114 / FDC2214 only)
0x13 SETTLECOUNT_CH3 0x0000 Channel 3 Settling Reference Count (FDC2114 / FDC2214 only)
0x14 CLOCK_DIVIDERS_CH0 0x0000 Reference divider settings for Channel 0
0x15 CLOCK_DIVIDERS_CH1 0x0000 Reference divider settings for Channel 1
0x16 CLOCK_DIVIDERS_CH2 0x0000 Reference divider settings for Channel 2 (FDC2114 / FDC2214 only)
0x17 CLOCK_DIVIDERS_CH3 0x0000 Reference divider settings for Channel 3 (FDC2114 / FDC2214 only)
0x18 STATUS 0x0000 Device Status Reporting
0x19 STATUS_CONFIG 0x0000 Device Status Reporting Configuration
0x1A CONFIG 0x2801 Conversion Configuration
0x1B MUX_CONFIG 0x020F Channel Multiplexing Configuration
0x1C RESET_DEV 0x0000 Reset Device
0x1E DRIVE_CURRENT_CH0 0x0000 Channel 0 sensor current drive configuration
0x1F DRIVE_CURRENT_CH1 0x0000 Channel 1 sensor current drive configuration
0x20 DRIVE_CURRENT_CH2 0x0000 Channel 2 sensor current drive configuration (FDC2114 / FDC2214 only)
0x21 DRIVE_CURRENT_CH3 0x0000 Channel 3 sensor current drive configuration (FDC2114 / FDC2214 only)
0x7E MANUFACTURER_ID 0x5449 Manufacturer ID
0x7F DEVICE_ID 0x3054 Device ID (FDC2112, FDC2114 only)
0x3055 Device ID (FDC2212, FDC2214 only)

7.6.2 Address 0x00, DATA_CH0

Figure 19. Address 0x00, DATA_CH0
15 14 13 12 11 10 9 8
RESERVED CH0_ERR_WD CH0_ERR_AW DATA0
7 6 5 4 3 2 1 0
DATA0

Table 12. Address 0x00, DATA_CH0 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R 00 Reserved.
13 CH0_ERR_WD R 0 Channel 0 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH0_ERR_AW R 0 Channel 0 Amplitude Warning. Cleared by reading the bit.
11:0 DATA0 (FDC2112 / FDC2114 only) R 0000 0000 0000 Channel 0 Conversion Result
DATA0[27:16] (FDC2212 / FDC2214 only)

7.6.3 Address 0x01, DATA_LSB_CH0 (FDC2212 / FDC2214 only)

Figure 20. Address 0x01, DATA_LSB_CH0
15 14 13 12 11 10 9 8
DATA0
7 6 5 4 3 2 1 0
DATA0

Table 13. Address 0x01, DATA_CH0 Field Descriptions

Bit Field Type Reset Description
15:0 DATA0[15:0] R 0000 0000 0000 Channel 0 Conversion Result

7.6.4 Address 0x02, DATA_CH1

Figure 21. Address 0x02, DATA_CH1
15 14 13 12 11 10 9 8
RESERVED CH1_ERR_WD CH1_ERR_AW DATA1
7 6 5 4 3 2 1 0
DATA1

Table 14. Address 0x02, DATA_CH1 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R 00 Reserved.
13 CH1_ERR_WD R 0 Channel 1 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH1_ERR_AW R 0 Channel 1 Amplitude Warning. Cleared by reading the bit.
11:0 DATA1 (FDC2112 / FDC2114 only) R 0000 0000 0000 Channel 1 Conversion Result
DATA1[27:16] (FDC2212 / FDC2214 only)

7.6.5 Address 0x03, DATA_LSB_CH1 (FDC2212 / FDC2214 only)

Figure 22. Address 0x03, DATA_LSB_CH1
15 14 13 12 11 10 9 8
DATA1
7 6 5 4 3 2 1 0
DATA1

Table 15. Address 0x03, DATA_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 DATA1[15:0] R 0000 0000 0000 Channel 1 Conversion Result

7.6.6 Address 0x04, DATA_CH2 (FDC2114, FDC2214 only)

Figure 23. Address 0x04, DATA_CH2
15 14 13 12 11 10 9 8
RESERVED CH2_ERR_WD CH2_ERR_AW DATA2
7 6 5 4 3 2 1 0
DATA2

Table 16. Address 0x04, DATA_CH2 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R 00 Reserved.
13 CH2_ERR_WD R 0 Channel 2 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH2_ERR_AW R 0 Channel 2 Amplitude Warning. Cleared by reading the bit.
11:0 DATA2 (FDC2112 / FDC2114 only) R 0000 0000 0000 Channel 2 Conversion Result
DATA2[27:16] (FDC2212 / FDC2214 only)

7.6.7 Address 0x05, DATA_LSB_CH2 (FDC2214 only)

Figure 24. Address 0x05, DATA_LSB_CH2
15 14 13 12 11 10 9 8
DATA2
7 6 5 4 3 2 1 0
DATA2

Table 17. Address 0x05, DATA_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 DATA2[15:0] R 0000 0000 0000 Channel 2 Conversion Result

7.6.8 Address 0x06, DATA_CH3 (FDC2114, FDC2214 only)

Figure 25. Address 0x06, DATA_CH3
15 14 13 12 11 10 9 8
RESERVED CH3_ERR_WD CH3_ERR_AW DATA3
7 6 5 4 3 2 1 0
DATA3

Table 18. Address 0x06, DATA_CH3 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R 00 Reserved.
13 CH3_ERR_WD R 0 Channel 3 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH3_ERR_AW R 0 Channel 3 Amplitude Warning. Cleared by reading the bit.
11:0 DATA3 (FDC2112 / FDC2114 only) R 0000 0000 0000 Channel 3 Conversion Result
DATA3[27:16] (FDC2212 / FDC2214 only)

7.6.9 Address 0x07, DATA_LSB_CH3 (FDC2214 only)

Figure 26. Address 0x07, DATA_LSB_CH3
15 14 13 12 11 10 9 8
DATA3
7 6 5 4 3 2 1 0
DATA3

Table 19. Address 0x07, DATA_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 DATA3[15:0] R 0000 0000 0000 Channel 3 Conversion Result

7.6.10 Address 0x08, RCOUNT_CH0

Figure 27. Address 0x08, RCOUNT_CH0
15 14 13 12 11 10 9 8
CH0_RCOUNT
7 6 5 4 3 2 1 0
CH0_RCOUNT

Table 20. Address 0x08, RCOUNT_CH0 Field Descriptions

Bit Field Type Reset Description
15:0 CH0_RCOUNT R/W 0000 0000 1000 0000 Channel 0 Reference Count Conversion Interval Time
0x0000-0x00FF: Reserved
0x0100-0xFFFF: Conversion Time (tC0) = (CH0_RCOUNTˣ16)/fREF0

7.6.11 Address 0x09, RCOUNT_CH1

Figure 28. Address 0x09, RCOUNT_CH1
15 14 13 12 11 10 9 8
CH1_RCOUNT
7 6 5 4 3 2 1 0
CH1_RCOUNT

Table 21. Address 0x09, RCOUNT_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 CH1_RCOUNT R/W 0000 0000 1000 0000 Channel 1 Reference Count Conversion Interval Time
0x0000-0x00FF: Reserved
0x0100-0xFFFF: Conversion Time (tC1)= (CH1_RCOUNTˣ16)/fREF1

7.6.12 Address 0x0A, RCOUNT_CH2 (FDC2114, FDC2214 only)

Figure 29. Address 0x0A, RCOUNT_CH2
15 14 13 12 11 10 9 8
CH2_RCOUNT
7 6 5 4 3 2 1 0
CH2_RCOUNT

Table 22. Address 0x0A, RCOUNT_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 CH2_RCOUNT R/W 0000 0000 1000 0000 Channel 2 Reference Count Conversion Interval Time
0x0000-0x00FF: Reserved
0x0100-0xFFFF: Conversion Time (tC2)= (CH2_RCOUNTˣ16)/fREF2

7.6.13 Address 0x0B, RCOUNT_CH3 (FDC2114, FDC2214 only)

Figure 30. Address 0x0B, RCOUNT_CH3
15 14 13 12 11 10 9 8
CH3_RCOUNT
7 6 5 4 3 2 1 0
CH3_RCOUNT

Table 23. Address 0x0B, RCOUNT_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 CH3_RCOUNT R/W 0000 0000 1000 0000 Channel 3 Reference Count Conversion Interval Time
0x0000-0x00FF: Reserved
0x0100-0xFFFF: Conversion Time (tC3)= (CH3_RCOUNTˣ16)/fREF3

7.6.14 Address 0x0C, OFFSET_CH0 (FDC21112 / FDC2114 only)

Figure 31. Address 0x0C, CH0_OFFSET
15 14 13 12 11 10 9 8
CH0_OFFSET
7 6 5 4 3 2 1 0
CH0_OFFSET

Table 24. CH0_OFFSET Field Descriptions

Bit Field Type Reset Description
15:0 CH0_OFFSET R/W 0000 0000 0000 0000 Channel 0 Conversion Offset. fOFFSET_0 = (CH0_OFFSET/216)*fREF0

7.6.15 Address 0x0D, OFFSET_CH1 (FDC21112 / FDC2114 only)

Figure 32. Address 0x0D, OFFSET_CH1
15 14 13 12 11 10 9 8
CH1_OFFSET
7 6 5 4 3 2 1 0
CH1_OFFSET

Table 25. Address 0x0D, OFFSET_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 CH1_OFFSET R/W 0000 0000 0000 0000 Channel 1 Conversion Offset. fOFFSET_1 = (CH1_OFFSET/216)*fREF1

7.6.16 Address 0x0E, OFFSET_CH2 (FDC2114 only)

Figure 33. Address 0x0E, OFFSET_CH2
15 14 13 12 11 10 9 8
CH2_OFFSET
7 6 5 4 3 2 1 0
CH2_OFFSET

Table 26. Address 0x0E, OFFSET_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 CH2_OFFSET R/W 0000 0000 0000 0000 Channel 2 Conversion Offset. fOFFSET_2 = (CH2_OFFSET/216)*fREF2

7.6.17 Address 0x0F, OFFSET_CH3 (FDC2114 only)

Figure 34. Address 0x0F, OFFSET_CH3
15 14 13 12 11 10 9 8
CH3_OFFSET
7 6 5 4 3 2 1 0
CH3_OFFSET

Table 27. Address 0x0F, OFFSET_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 CH3_OFFSET R/W 0000 0000 0000 0000 Channel 3 Conversion Offset. fOFFSET_3 = (CH3_OFFSET/216)*fREF3

7.6.18 Address 0x10, SETTLECOUNT_CH0

Figure 35. Address 0x10, SETTLECOUNT_CH0
15 14 13 12 11 10 9 8
CH0_SETTLECOUNT
7 6 5 4 3 2 1 0
CH0_SETTLECOUNT

Table 28. Address 0x11, SETTLECOUNT_CH0 Field Descriptions

Bit Field Type Reset Description
15:0 CH0_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 0 Conversion Settling
The FDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on Channel 0.
If the amplitude has not settled prior to the conversion start, an Amplitude warning will be generated if reporting of this type of warning is enabled.
0x0000: Settle Time (tS0)= 32 ÷ fREF0
0x0001: Settle Time (tS0)= 32 ÷ fREF0
0x0002 - 0xFFFF: Settle Time (tS0)= (CH0_SETTLECOUNTˣ16) ÷ fREF0

7.6.19 Address 0x11, SETTLECOUNT_CH1

Figure 36. Address 0x11, SETTLECOUNT_CH1
15 14 13 12 11 10 9 8
CH1_SETTLECOUNT
7 6 5 4 3 2 1 0
CH1_SETTLECOUNT

Table 29. Address 0x12, SETTLECOUNT_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 CH1_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 1 Conversion Settling
The FDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on a Channel 1.
If the amplitude has not settled prior to the conversion start, an Amplitude warning will be generated if reporting of this type of warning is enabled.
0x0000: Settle Time (tS1)= 32 ÷ fREF1
0x0001: Settle Time (tS1)= 32 ÷ fREF1
0x0002 - 0xFFFF: Settle Time (tS1)= (CH1_SETTLECOUNTˣ16) ÷ fREF1

7.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114, FDC2214 only)

Figure 37. Address 0x12, SETTLECOUNT_CH2
15 14 13 12 11 10 9 8
CH2_SETTLECOUNT
7 6 5 4 3 2 1 0
CH2_SETTLECOUNT

Table 30. Address 0x12, SETTLECOUNT_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 CH2_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 2 Conversion Settling
The FDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on Channel 2.
If the amplitude has not settled prior to the conversion start, an Amplitude warning will be generated if reporting of this type of warning is enabled.
0x0000: Settle Time (tS2) = 32 ÷ fREF2
0x0001: Settle Time (tS2) = 32 ÷ fREF2
0x0002 - 0xFFFF: Settle Time (tS2)= (CH2_SETTLECOUNTˣ16) ÷ fREF2

7.6.21 Address 0x13, SETTLECOUNT_CH3 (FDC2114, FDC2214 only)

Figure 38. Address 0x13, SETTLECOUNT_CH3
15 14 13 12 11 10 9 8
CH3_SETTLECOUNT
7 6 5 4 3 2 1 0
CH3_SETTLECOUNT

Table 31. Address 0x13, SETTLECOUNT_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 CH3_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 3 Conversion Settling
The FDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on Channel 3.
If the amplitude has not settled prior to the conversion start, an Amplitude warning will be generated if reporting of this type of warning is enabled
0x0000: Settle Time (tS3) = 32 ÷ fREF3
0x0001: Settle Time (tS3) = 32 ÷ fREF3
0x0002 - 0xFFFF: Settle Time (tS3)= (CH3_SETTLECOUNTˣ16) ÷ fREF3

7.6.22 Address 0x14, CLOCK_DIVIDERS_CH0

Figure 39. Address 0x14, CLOCK_DIVIDERS_CH0
15 14 13 12 11 10 9 8
RESERVED CH0_FIN_SEL RESERVED CH0_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH0_FREF_DIVIDER

Table 32. Address 0x14, CLOCK_DIVIDERS_CH0 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R/W 00 Reserved. Set to b00.
13:12 CH0_FIN_SEL R/W 00 Channel 0 Sensor frequency select
for differential sensor configuration:
b01: divide by 1. Choose for sensor frequencies between 0.01 MHz and 8.75 MHz
b10: divide by 2. Choose for sensor frequencies between 5 MHz and 10 MHz

for single-ended sensor configuration:
b10: divide by 2. Choose for sensor frequencies between 0.01 MHz and 10 MHz
11:10 RESERVED R/W 00 Reserved. Set to b00.
9:0 CH0_FREF_DIVIDER R/W 00 0000 0000 Channel 0 Reference Divider
Sets the divider for Channel 0 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH0_FREF_DIVIDER≥b00’0000’0001: fREF0 = fCLK/CH0_FREF_DIVIDER

7.6.23 Address 0x15, CLOCK_DIVIDERS_CH1

Figure 40. Address 0x15, CLOCK_DIVIDERS_CH1
15 14 13 12 11 10 9 8
RESERVED CH1_FIN_SEL RESERVED CH1_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH1_FREF_DIVIDER

Table 33. Address 0x15, CLOCK_DIVIDERS_CH1 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R/W 00 Reserved. Set to b00.
13:12 CH1_FIN_SEL R/W 0000 Channel 1 Sensor frequency select
for differential sensor configuration:
b01: divide by 1. Choose for sensor frequencies between 0.01 MHz and 8.75 MHz
b10: divide by 2. Choose for sensor frequencies between 5 MHz and 10 MHz

for single-ended sensor configuration:
b10: divide by 2. Choose for sensor frequencies between 0.01 MHz and 10 MHz
11:10 RESERVED R/W 00 Reserved. Set to b00.
9:0 CH1_FREF_DIVIDER R/W 00 0000 0000 Channel 1 Reference Divider
Sets the divider for Channel 1 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH1_FREF_DIVIDER≥ b00’0000’0001: fREF1 = fCLK/CH1_FREF_DIVIDER

7.6.24 Address 0x16, CLOCK_DIVIDERS_CH2 (FDC2114, FDC2214 only)

Figure 41. Address 0x16, CLOCK_DIVIDERS_CH2
15 14 13 12 11 10 9 8
RESERVED CH2_FIN_SEL RESERVED CH2_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH2_FREF_DIVIDER

Table 34. Address 0x16, CLOCK_DIVIDERS_CH2 Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R/W 00 Reserved. Set to b00.
13:12 CH2_FIN_SEL R/W 0000 Channel 2 Sensor frequency select
for differential sensor configuration:
b01: divide by 1. Choose for sensor frequencies between 0.01 MHz and 8.75 MHz
b10: divide by 2. Choose for sensor frequencies between 5 MHz and 10 MHz

for single-ended sensor configuration:
b10: divide by 2. Choose for sensor frequencies between 0.01 MHz and 10 MHz
11:10 RESERVED R/W 00 Reserved. Set to b00.
9:0 CH2_FREF_DIVIDER R/W 00 0000 0000 Channel 2 Reference Divider
Sets the divider for Channel 2 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH2_FREF_DIVIDER ≥ b00’0000’0001: fREF2 = fCLK/CH2_FREF_DIVIDER

7.6.25 Address 0x17, CLOCK_DIVIDERS_CH3 (FDC2114, FDC2214 only)

Figure 42. Address 0x17, CLOCK_DIVIDERS_CH3
15 14 13 12 11 10 9 8
RESERVED CH3_FIN_SEL RESERVED CH3_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH3_FREF_DIVIDER

Table 35. Address 0x17, CLOCK_DIVIDERS_CH3

Bit Field Type Reset Description
15:14 RESERVED R/W 00 Reserved. Set to b00.
13:12 CH3_FIN_SEL R/W 0000 Channel 3 Sensor frequency select
for differential sensor configuration:
b01: divide by 1. Choose for sensor frequencies between 0.01 MHz and 8.75 MHz
b10: divide by 2. Choose for sensor frequencies between 5 MHz and 10 MHz

for single-ended sensor configuration:
b10: divide by 2. Choose for sensor frequencies between 0.01 MHz and 10 MHz
11:10 RESERVED R/W 00 Reserved. Set to b00.
9:0 CH3_FREF_DIVIDER R/W 00 0000 0000 Channel 3 Reference Divider
Sets the divider for Channel 3 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: reserved
CH3_FREF_DIVIDER ≥ b00’0000’0001: fREF3 = fCLK/CH3_FREF_DIVIDER

7.6.26 Address 0x18, STATUS

Figure 43. Address 0x18, STATUS
15 14 13 12 11 10 9 8
ERR_CHAN RESERVED ERR_WD RESERVED
7 6 5 4 3 2 1 0
RESERVED DRDY RESERVED CH0_UNREADCONV CH1_ UNREADCONV CH2_ UNREADCONV CH3_ UNREADCONV

Table 36. Address 0x18, STATUS Field Descriptions

Bit Field Type Reset Description
15:14 ERR_CHAN R 00 Error Channel
Indicates which channel has generated a Flag or Error. Once flagged, any reported error is latched and maintained until either the STATUS register or the DATA_CHx register corresponding to the Error Channel is read.
b00: Channel 0 is source of flag or error.
b01: Channel 1 is source of flag or error.
b10: Channel 2 is source of flag or error (FDC2114, FDC2214 only).
b11: Channel 3 is source of flag or error (FDC2114, FDC2214 only).
13:12 RESERVED R 00 Reserved
11 ERR_WD R 0 Watchdog Timeout Error
b0: No Watchdog Timeout error was recorded since the last read of the STATUS register.
b1: An active channel has generated a Watchdog Timeout error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
10 ERR_AHW R 0 Amplitude High Warning
b0: No Amplitude High warning was recorded since the last read of the STATUS register.
b1: An active channel has generated an Amplitude High warning. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this warning.
9 ERR_ALW R 0 Amplitude Low Warning
b0: No Amplitude Low warning was recorded since the last read of the STATUS register.
b1: An active channel has generated an Amplitude Low warning. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this warning.
8:7 RESERVED R 00 Reserved
6 DRDY R 0 Data Ready Flag.
b0: No new conversion result was recorded in the STATUS register.
b1: A new conversion result is ready. When in Single Channel Conversion, this indicates a single conversion is available. When in sequential mode, this indicates that a new conversion result for all active channels is now available.
3 CH0_UNREADCONV R 0 Channel 0 Unread Conversion b0: No unread conversion is present for Channel 0.
b1: An unread conversion is present for Channel 0.
Read Register DATA_CH0 to retrieve conversion results.
2 CH1_ UNREADCONV R 0 Channel 1 Unread Conversion b0: No unread conversion is present for Channel 1.
b1: An unread conversion is present for Channel 1.
Read Register DATA_CH1 to retrieve conversion results.
1 CH2_ UNREADCONV R 0 Channel 2 Unread Conversion b0: No unread conversion is present for Channel 2.
b1: An unread conversion is present for Channel 2.
Read Register DATA_CH2 to retrieve conversion results (FDC2114, FDC2214 only)
0 CH3_ UNREADCONV R 0 Channel 3 Unread Conversion
b0: No unread conversion is present for Channel 3.
b1: An unread conversion is present for Channel 3.
Read Register DATA_CH3 to retrieve conversion results (FDC2114, FDC2214 only)

7.6.27 Address 0x19, ERROR_CONFIG

Figure 44. Address 0x19, ERROR_CONFIG
15 14 13 12 11 10 9 8
RESERVED WD_ ERR2OUT AH_WARN2OUT AL_WARN2OUT RESERVED
7 6 5 4 3 2 1 0
RESERVED WD_ERR2INT RESERVED DRDY_2INT

Table 37. Address 0x19, ERROR_CONFIG

Bit Field Type Reset Description
15:14 RESERVED R/W 00 Reserved (set to b000)
13 WD_ ERR2OUT R/W 0 Watchdog Timeout Error to Output Register
b0: Do not report Watchdog Timeout errors in the DATA_CHx registers.
b1: Report Watchdog Timeout errors in the DATA_CHx.CHx_ERR_WD register field corresponding to the channel that generated the error.
12 AH_WARN2OUT R/W 0 Amplitude High Warning to Output Register
b0:Do not report Amplitude High warnings in the DATA_CHx registers.
b1: Report Amplitude High warnings in the DATA_CHx.CHx_ERR_AW register field corresponding to the channel that generated the warning.
11 AL_WARN2OUT R/W 0 Amplitude Low Warning to Output Register
b0: Do not report Amplitude Low warnings in the DATA_CHx registers.
b1: Report Amplitude High warnings in the DATA_CHx.CHx_ERR_AW register field corresponding to the channel that generated the warning.
10:6 RESERVED R/W 0 0000 Reserved (set to b0 0000)
5 WD_ERR2INT R/W 0 Watchdog Timeout Error to INTB b0: Do not report Under-range errors by asserting INTB pin and STATUS register.
b1: Report Watchdog Timeout errors by asserting INTB pin and updating STATUS.ERR_WD register field.
4:1 Reserved R/W 0000 Reserved (set to b000)
0 DRDY_2INT R/W 0 Data Ready Flag to INTB b0: Do not report Data Ready Flag by asserting INTB pin and STATUS register.
b1: Report Data Ready Flag by asserting INTB pin and updating STATUS. DRDY register field.

7.6.28 Address 0x1A, CONFIG

Figure 45. Address 0x1A, CONFIG
15 14 13 12 11 10 9 8
ACTIVE_CHAN SLEEP_MODE_EN RESERVED SENSOR_ACTIVATE_SEL RESERVED REF_CLK_SRC RESERVED
7 6 5 4 3 2 1 0
INTB_DIS HIGH_CURRENT_DRV RESERVED

Table 38. Address 0x1A, CONFIG Field Descriptions

Bit Field Type Reset Description
15:14 ACTIVE_CHAN R/W 00 Active channel selection
Selects channel for continuous conversions when MUX_CONFIG.SEQUENTIAL is 0.
b00: Perform continuous conversions on Channel 0
b01: Perform continuous conversions on Channel 1
b10: Perform continuous conversions on Channel 2 (FDC2114, FDC2214 only)
b11: Perform continuous conversions on Channel 3 (FDC2114, FDC2214 only)
13 SLEEP_MODE_EN R/W 1 Sleep mode enable
Enter or exit low power sleep mode.
b0: Device is active.
b1: Device is in sleep mode.
12 RESERVED R/W 0 Reserved. Set to b1.
11 SENSOR_ACTIVATE_SEL R/W 1 Sensor activation mode selection.
Set the mode for sensor initialization.
b0: Full current activation mode – the FDC will drive maximum sensor current for a shorter sensor activation time.
b1: Low power activation mode – the FDC uses the value programmed in DRIVE_CURRENT_CHx during sensor activation to minimize power consumption.
10 RESERVED R/W 0 Reserved. Set to b1.
9 REF_CLK_SRC R/W 0 Select Reference Frequency Source
b0: Use Internal oscillator as reference frequency
b1: Reference frequency is provided from CLKIN pin.
8 RESERVED R/W 0 Reserved. Set to b0.
7 INTB_DIS R/W 0 INTB Disable
b0: INTB pin is asserted when status register updates.
b1: INTB pin is not asserted when status register updates
6 HIGH_CURRENT_DRV R/W 0 High Current Sensor Drive
b0: The FDC drives all channels with normal sensor current (1.5 mA maximum).
b1: The FDC drives channel 0 with current >1.5 mA.
This mode is not supported if AUTOSCAN_EN = b1 (multi-channel mode)
5:0 RESERVED R/W 00 0001 Reserved Set to b00’0001

7.6.29 Address 0x1B, MUX_CONFIG

Figure 46. Address 0x1B, MUX_CONFIG
15 14 13 12 11 10 9 8
AUTOSCAN_EN RR_SEQUENCE RESERVED
7 6 5 4 3 2 1 0
RESERVED DEGLITCH

Table 39. Address 0x1B, MUX_CONFIG Field Descriptions

Bit Field Type Reset Description
15 AUTOSCAN_EN R/W 0 Auto-Scan mode enable
b0: Continuous conversion on the single channel selected by CONFIG.ACTIVE_CHAN register field.
b1: Auto-Scan conversions as selected by MUX_CONFIG.RR_SEQUENCE register field.
14:13 RR_SEQUENCE R/W 00 Auto-Scan sequence configuration
Configure multiplexing channel sequence. The FDC performs a single conversion on each channel in the sequence selected, and then restart the sequence continuously.
b00: Ch0, Ch1
b01: Ch0, Ch1, Ch2 (FDC2114, FDC2214 only)
b10: Ch0, Ch1, Ch2, Ch3 (FDC2114, FDC2214 only)
b11: Ch0, Ch1
12:3 RESERVED R/W 00 0100 0001 Reserved. Must be set to 00 0100 0001
2:0 DEGLITCH R/W 111 Input deglitch filter bandwidth.
Select the lowest setting that exceeds the oscillation tank oscillation frequency.
b001: 1 MHz
b100: 3.3 MHz
b101: 10 MHz
b111: 33 MHz

7.6.30 Address 0x1C, RESET_DEV

Figure 47. Address 0x1C, RESET_DEV
15 14 13 12 11 10 9 8
RESET_DEV RESERVED OUTPUT_GAIN RESERVED
7 6 5 4 3 2 1 0
RESERVED

Table 40. Address 0x1C, RESET_DEV Field Descriptions

Bit Field Type Reset Description
15 RESET_DEV R/W 0 Device Reset
Write b1 to reset the device. Will always readback 0.
14:11 RESERVED R/W 0000 Reserved. Set to b0000
10:9 OUTPUT_GAIN R/W 00 Output gain control (FDC2112, FDC2114 only)
00: Gain =1 (0 bits shift)
01: Gain = 4 (2 bits shift)
10: Gain = 8 (3 bits shift)
11: Gain = 16 (4 bits shift)
8:0 RESERVED R/W 0 0000 0000 Reserved, Set to b0 0000 0000

7.6.31 Address 0x1E, DRIVE_CURRENT_CH0

Figure 48. Address 0x1E, DRIVE_CURRENT_CH0
15 14 13 12 11 10 9 8
CH0_IDRIVE RESERVED
7 6 5 4 3 2 1 0
RESERVED

Table 41. Address 0x1E, DRIVE_CURRENT_CH0 Field Descriptions

Bit Field Type Reset Description
15:11 CH0_IDRIVE R/W 0000 0 Channel 0 Sensor drive current
This field defines the Drive Current used during the settling + conversion time of Channel 0 sensor clock. Set such that 1.2V ≤ sensor oscillation amplitude (pk) ≤ 1.8V
00000: 0.016 mA
00001: 0.018 mA
00010: 0.021 mA
00011: 0.025 mA
00100: 0.028 mA
00101: 0.033 mA
00110: 0.038 mA
00111: 0.044 mA
01000: 0.052 mA
01001: 0.060 mA
01010: 0.069 mA
01011: 0.081 mA
01100: 0.093 mA
01101: 0.108 mA
01110: 0.126 mA
01111: 0.146 mA
10000: 0.169 mA
10001: 0.196 mA
10010: 0.228 mA
10011: 0.264 mA
10100: 0.307 mA
10101: 0.356 mA
10110: 0.413 mA
10111: 0.479 mA
11000: 0.555 mA
11001: 0.644 mA
11010: 0.747 mA
11011: 0.867 mA
11100: 1.006 mA
11101: 1.167 mA
11110: 1.354 mA
11111: 1.571 mA
10:0 RESERVED – 000 0000 0000 Reserved

7.6.32 Address 0x1F, DRIVE_CURRENT_CH1

Figure 49. Address 0x1F, DRIVE_CURRENT_CH1
15 14 13 12 11 10 9 8
CH1_IDRIVE RESERVED
7 6 5 4 3 2 1 0
RESERVED

Table 42. Address 0x1F, DRIVE_CURRENT_CH1 Field Descriptions

Bit Field Type Reset Description
15:11 CH1_IDRIVE R/W 0000 0 Channel 1 Sensor drive current
This field defines the drive current used during the settling + conversion time of Channel 1 sensor clock. Set such that 1.2 V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
00000: 0.016 mA
00001: 0.018 mA
00010: 0.021 mA
...
11111: 1.571 mA
10:0 RESERVED - 000 0000 0000 Reserved

7.6.33 Address 0x20, DRIVE_CURRENT_CH2 (FDC2114 / FDC2214 only)

Figure 50. Address 0x20, DRIVE_CURRENT_CH2
15 14 13 12 11 10 9 8
CH2_IDRIVE RESERVED
7 6 5 4 3 2 1 0
RESERVED

Table 43. Address 0x20, DRIVE_CURRENT_CH2 Field Descriptions

Bit Field Type Reset Description
15:11 CH2_IDRIVE R/W 0000 0 Channel 2 Sensor drive current
This field defines the drive current to be used during the settling + conversion time of Channel 2 sensor clock. Set such that 1.2 V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
00000: 0.016 mA
00001: 0.018 mA
00010: 0.021 mA
...
11111: 1.571 mA
10:0 RESERVED – 000 0000 0000 Reserved

7.6.34 Address 0x21, DRIVE_CURRENT_CH3 (FDC2114 / FDC2214 only)

Figure 51. Address 0x21, DRIVE_CURRENT_CH3
15 14 13 12 11 10 9 8
CH3_IDRIVE RESERVED
7 6 5 4 3 2 1 0
RESERVED

Table 44. DRIVE_CURRENT_CH3 Field Descriptions

Bit Field Type Reset Description
15:11 CH3_IDRIVE R/W 0000 0 Channel 3 Sensor drive current
This field defines the drive current to be used during the settling + conversion time of Channel 3 sensor clock. Set such that 1.2V ≤ sensor oscillation amplitude (pk) ≤ 1.8 V
00000: 0.016 mA
00001: 0.018 mA
00010: 0.021 mA
...
11111: 1.571 mA
10:0 RESERVED – 000 0000 0000 Reserved

7.6.35 Address 0x7E, MANUFACTURER_ID

Figure 52. Address 0x7E, MANUFACTURER_ID
15 14 13 12 11 10 9 8
MANUFACTURER_ID
7 6 5 4 3 2 1 0
MANUFACTURER_ID

Table 45. Address 0x7E, MANUFACTURER_ID Field Descriptions

Bit Field Type Reset Description
15:0 MANUFACTURER_ID R 0101 0100 0100 1001 Manufacturer ID = 0x5449

7.6.36 Address 0x7F, DEVICE_ID

Figure 53. Address 0x7F, DEVICE_ID
7 6 5 4 3 2 1 0
DEVICE_ID

Table 46. Address 0x7F, DEVICE_ID Field Descriptions

Bit Field Type Reset Description
7:0 DEVICE_ID R 0011 0000 0101 0100 Device ID
0x3054 (FDC2112, FDC2114 only)
0x3055 (FDC2212, FDC2214 only)
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