The multi-channel package of the FDC enables the user to save board space and support flexible system design. For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant frequency of the sensor. Using a second sensor as a reference provides the capability to cancel out a temperature shift. When operated in multi-channel mode, the FDC sequentially samples the active channels. In single-channel mode, the FDC samples a single channel, which is selectable. Table 6-3 shows the registers and values that are used to configure either multi-channel or single-channel modes.

The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the reference frequency.

The data output (DATAx) of the FDC2112 and FDC2114 is expressed as the 12 MSBs of a 16-bit result:

Equation 1.

The data output (DATAx) of the FDC2212 and FDC2214 is expressed as:

Equation 2.

Table 6-4 lists the registers that contain the fixed point sample values for each channel.

When the FDC sequences through the channels in multi-channel mode, the dwell time interval for each channel is the sum of three parts:

1. sensor activation time
2. conversion time
3. channel switch delay

The sensor activation time is the amount of settling time required for the sensor oscillation to stabilize, as shown in Figure 6-4. The settling wait time is programmable, and TI recommends setting the wait time to a value that is long enough to allow stable oscillation. The settling wait time for channel x is given by:

Table 6-5 illustrates the registers and values for configuring the settling time for each channel.

Figure 6-4 Multi-Channel Mode Sequencing

Figure 6-5 Single-Channel Mode Sequencing

The SETTLECOUNT for any channel x must satisfy:

• Equation 4. CHx_SETTLECOUNT > V_pk × f_REFx × C × π² / (32 × IDRIVE_X)

• • where

  • V_pk = Peak oscillation amplitude at the programmed IDRIVE setting
  • f_REFx = Reference frequency for Channel x
  • C = sensor capacitance including parasitic PCB capacitance
  • IDRIVE_X = setting programmed into the IDRIVE register in amps

• Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08, program the register to 7 or higher).

• The conversion time represents the number of reference clock cycles used to measure the sensor frequency and is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:

• Equation 5. t_Cx = (CHx_RCOUNT × 16 + 4) /f_REFx

• The reference count value must be chosen to support the required number of effective bits (ENOB). For example, if an ENOB of 13 bits is required, then a minimum conversion time of 2¹³ = 8192 clock cycles is required. 8192 clock cycles correspond to a CHx_RCOUNT value of 0x0200.

The typical channel switch delay time between the end of conversion and the beginning of sensor activation of the subsequent channel is:

The deterministic conversion time of the FDC allows data polling at a fixed interval. For example, if the programmed SETTLECOUNT is 128 F_REF cycles (SETTLECOUNT = 0x0008) and RCOUNT is 512 F_REF cycles (RCOUNT=0x0020), then one conversion takes 3.2ms (sensor-activation time) + 12.8ms (conversion time) + 0.8µs (channel-switch delay) = 16.0ms per channel. If the FDC is configured for dual-channel operation by setting AUTOSCAN_EN = 1 and RR_SEQUENCE = 00, then one full set of conversion results is available from the data registers every 32ms.

A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register description in Register Maps.