ZHCSUH8B December 2017 – January 2024 FPC202
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Host-Side Control Interface
- 7.3.2 LED Control
- 7.3.3 Low-Speed Output Signal Control
- 7.3.4 Low-Speed Input Status and Interrupt Generation
- 7.3.5 Downstream (Port-Side) I2C Master
- 7.3.6 Data Pre-Fetch From Modules
- 7.3.7 Scheduled Write
- 7.3.8 Protocol Timeouts
- 7.3.9 General-Purpose Inputs/Outputs
- 7.3.10 Hot-Plug Support
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.4.2 SPI Host-Side Control Interface
If SPI is used as the host-side communication protocol, the maximum number of FPC202 devices which can share a single SPI bus is technically unlimited. The read and write latency from/to the downstream ports will increase as the length of the SPI chain increases.
SPI does not require each FPC202 to have an address. The FPC202 devices are connected in a daisy-chain fashion as shown in Figure 7-6. The first FPC202 will connect CTRL3 (MOSI) to the host controller’s MOSI signal. CTRL4 (MISO) on the first FPC202 will connect to the subsequent FPC202’s CTRL3 (MOSI) signal and so on until the final FPC202’s CTRL4 (MISO) signal connects back to the host controller’s MISO signal. All FPC202’s will connect CTRL1 (SCK) and CTRL2 (SS_N) to the same SCK and SS_N pin on the host controller. For LED blink synchronization across multiple FPC202 devices, the SPI_LED_SYNC pin should be connected across all FPC202 devices in SPI mode. This is not necessary in I2C mode.
Each FPC202 device in the SPI chain will capture and act upon the command in its shift register when SS_N transitions from low (0) to high (1). The MOSI input is ignored and the MISO output is high impedance whenever SS_N is de-asserted high.
The prior SPI command, address, and data are shifted out on MISO as the current SPI command, address, and data are shifted in on MOSI. In all SPI transactions, the MISO output signal is enabled asynchronously whenever SS_N is asserted low.
Figure 7-6 FPC202 Connection Diagram For SPI ModeThe SPI address space for FPC202 applications is designed such that each port being controlled and each logical device address within each port is accessible to the host controller through a unique 12-bit address. For a system with up to N FPC202 devices on a single SPI chain, the full SPI address map is shown in Table 7-7.
| FPC202 INSTANCE NUMBER | ADDRESS RANGE | ||||
|---|---|---|---|---|---|
| PORT 0 | PORT 1 | FPC202 REGS | |||
| PRIMARY DEVICE Default = 0xA0(1) | SECONDARY DEVICE Default = 0xA0(1) | PRIMARY DEVICE Default = 0xA0(1) | SECONDARY DEVICE Default = 0xA0(1) | ||
| 0 | 0x000 to 0x0FF | 0x100 to 0x1FF | 0x400 to 0x4FF | 0x500 to 0x5FF | 0x800 to 0x8FF |
| 1 | |||||
| 2 | |||||
| – | |||||
| N | |||||
In SPI mode, the CTRL4 pin has a driver impedance of 60 Ω (typical). In order to minimize ringing due to the fast edge rate of the driver, it is recommended to match the transmission line characteristic impedance with the driver impedance. A series resistor near the driver pin (CTRL4) may be used to facilitate this impedance matching. If ringing is a concern, the IBIS model provided may be used for simulations.