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ZHCSUH8B December 2017 – January 2024 FPC202

PRODUCTION DATA

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6.6 Timing Requirements

			MIN	NOM	MAX	UNIT
GENERAL TIMING REQUIREMENTS
T_POR	Internal power-on reset (PoR) time	Time between stable VDD1 power supply (VDD1 ≥ 3.3V - 5%) and de-assertion of internal PoR. The port-side and host-side control interfaces (I2C and/or SPI) are not operational during this time.	30		50	ms
HOST-SIDE SPI TIMING REQUIREMENTS (PROTOCOL_SEL =GND) ⁽¹⁾⁽²⁾
f_SPI			0.1		10	MHz
t_HI-SCK				0.4 ÷ f_SPI		ns
t_LO-SCK				0.4 ÷ f_SPI		ns
t_HD-MOSI				1		ns
t_SU-MOSI				1		ns
t_HD-SSN				4		ns
t_SU-SSN				1.2		ns
t_OFF-SSN		For writes and local FPC202 register reads		1		μs
		For consecutive downstream (remote) register reads on the same port, assuming 400 KHz I2C		170
		For consecutive downstream (remote) register reads on the same port, assuming 100 KHz I2C		620
t_ODZ-MISO	MISO (CTRL4) driven-to-TRI_STATE time			32		ns
t_OZD-MISO	MISO (CTRL4) TRI_STATE-to-driven time			10		ns
t_OD	MISO (CTRL4) output delay time			15		ns
HOST-SIDE I2C TIMING REQUIREMENTS (PROTOCOL_SEL=FLOAT OR HIGH)⁽²⁾⁽³⁾⁽⁴⁾
f_SCL	Host-side I2C clock frequency (CTRL1) in I2C mode		100		1000	kHz
t_BUF	Bus free time between STOP and START condition		0.5			μs
t_HD-STA	Hold time after (repeated) START condition. After this period, the first clock is generated.	After this period, the first clock can be generated by the master.	0.3			μs
t_SU-STA	Repeated START condition setup time		0.3			μs
t_SU-STO	STOP condition setup time		0.3			μs
t_HD-DAT	SDA (CTRL2) hold time		32			ns
t_SU-DAT	SDA (CTRL2) setup time	Applies to standard-mode I2C, 100 kHz	250			ns
	SDA (CTRL2) setup time	Applies to fast-mode I2C, 400 kHz	100			ns
	SDA (CTRL2) setup time	Applies to fast-mode plus I2C, 1000 kHz	50			ns
t_LOW	SCL (CTRL1) clock low time		0.5			μs
t_HIGH	SCL (CTRL1) clock high time		0.3			μs
t_R	SDA (CTRL2) rise time, read	Applies to standard-mode I2C, 100 kHz			1000	ns
	SDA (CTRL2) rise time, read	Applies to fast-mode I2C, 400 kHz	20		300	ns
	SDA (CTRL2) rise time, read	Applies to fast-mode plus I2C, 1000 kHz			120	ns
t_F	SDA (CTRL2) fall time, read	Applies to standard-mode I2C, 100 kHz			300	ns
	SDA (CTRL2) fall time, read	Applies to fast-mode I2C, 400 kHz	4.4		300	ns
	SDA (CTRL2) fall time, read	Applies to fast-mode plus I2C, 1000 kHz	4.4		120	ns

(1) SPI operation is available T_POR milliseconds after VDD1 power up, provided EN = high or float and VDD2 is stable.

(2) These parameters are not production tested.

(3) I2C operation is available T_POR milliseconds after VDD1 power up, provided EN = high or float and VDD2 is stable.

(4) These specifications support I2C Rev 6 specifications