The design procedure for SFP/QSFP applications is as follows:

1. Determine the total number of ports in the system, N_ports, which require management through an FPC202 device. The minimum number of FPC202 devices required to support N_ports is ceiling{N_ports÷2}.
2. Determine which host-side control interface will be used to manage all FPC202 devices and all ports: I2C or SPI.
3. For I2C applications:
   1. Up to 14 FPC202 devices can share a single host-side I2C control bus. If more than 14 FPC202 devices are used, then more than one I2C control bus will be required.
   2. Care should be taken to make sure the I2C clock (SCL) and data (SDA) lines do not exceed the maximum bus capacitance defined in Section 6.5. The bus capacitance will consist of the pin capacitance from each device connected plus the trace capacitance.
   3. Make sure appropriate pull-up resistors are selected for the I2C clock (SCL) and data (SDA) lines.
4. For SPI applications:
   1. When using SPI for host-side communications, technically there is no limit to the number of FPC202 devices which can exist on the SPI chain. However, the user should be aware that for SPI communication, skew is introduced between the SCK and MISO lines due to the propagation delay of the data through all of the devices and trace and then back to the host. It is up to the user to ensure that host's SPI timings are met after any skew due to propagation delay.
   2. Care should be taken to make sure the SPI clock (SCK) and data (MOSI and MISO) lines do not exceed the maximum bus capacitance defined in Section 6.5. The bus capacitance will consist of the pin capacitance from each device connected plus the trace capacitance.
5. Route the low-speed inputs (P[1:0]_S*_IN_*), outputs (P[1:0]_S*_OUT_*), and I2C signals (P[1:0]_MOD_SCL / P[1:0]_MOD_SDA) from the FPC202 to the corresponding port or device, keeping all the signals for a given port grouped together. For example, if FPC202 port 1 is being used to control QSFP port 7, then all of QSFP port 7’s low-speed signals, LED signals, and I2C signals should connect to FPC202 pins P1_S*_IN_*, P1_S*_OUT_*, and P1_MOD_SCL/P1_MOD_SDA.
6. Utilize the spare S*_IN_*, S*_OUT_*, and GPIO[3:0] signals to control miscellaneous functions on the board, like enabling and disabling a power switch.
7. For applications requiring hot-plug between the FPC202 and the host controller, control the FPC202 enable signal (EN, pin 22) such that EN is de-asserted low until VDD2 and the host-side control interface (I2C or SPI) is fully connected and stable.