ZHCSLX3C June 2017 – September 2020 FPC402
PRODUCTION DATA
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
DOWNSTREAM MASTER I2C SWITCHING CHARACTERISTICS | ||||||
fSCL | SCL clock frequency | Applies to standard-mode I2C, 100 kHz | 66 | 83 | 100 | kHz |
Applies to fast-mode I2C, 400 kHz | 264 | 332 | 400 | |||
tLOW-SCL | SCL clock pulse width low period | 1.3 | μs | |||
tHIGH-SCL | SCL clock pulse width high period | 0.6 | μs | |||
tBUF | Time bus free before new transmission starts | Between STOP and START and between ACK and RESTART | 20 | μs | ||
tHD-STA | Hold time START operation | 0.6 | μs | |||
tSU-STA | Setup time START operation | 0.6 | μs | |||
tHD-DAT | Data hold time | 0 | μs | |||
tSU-DAT | Data setup time | 0 | μs | |||
tR | SCL and SDA rise time | 100-KHz operation. From VIL (Max) – 0.15 V to VIH (Min) + 0.15 V. | 300 | ns | ||
100-KHz operation. From VIL (Max) – 0.15 V to VIH (Min) + 0.15 V. | 300 | |||||
tF | SCL and SDA fall time | 100-KHz operation. From VIH (Min) + 0.15 V to VIL (Max) – 0.15 V. | 300 | ns | ||
400-KHz operation. From VIH (Min) + 0.15 V to VIL (Max) – 0.15 V. | 300 | |||||
tSU-STO | STOP condition setup time | 0.6 | μs | |||
tSP-I2C(1) | Pulse width of spikes that are suppressed by FPC402 input filter | 0 | 50 | ns |