If I2C is used as the host-side communication protocol, the maximum number of FPC402 devices which can share a single I2C bus is 14. This allows for controlling up to 56 downstream ports through a single I2C bus.

I2C is an addressed interface. To reduce pin count and simplify integration, the FPC402 has an auto-addressing scheme whereby all FPC402s in a system will take on a unique address without requiring dedicated address pins. This is accomplished by connecting one CTRL4 (ADDR_DONE_N) pin of a FPC402 device to the subsequent CTRL3 (SET_ADDR_N) pin of another FPC402 device. The first FPC402 will connect CTRL3 (SET_ADDR_N) to GND, and the final FPC402 will connect CTRL4 (ADDR_DONE_N) to GND, as shown in Figure 8-4.

Figure 8-4 FPC402 Connection Diagram for Unique Addressing in I2C Mode

For I2C host-side control interface implementations, the host controller must first configure each FPC402 device to have a unique address. The CTRL3 (SET_ADDR_N) pin is internally pulled to high logic (regardless of the EN pin status) and the FPC402 device will not respond to any I2C transactions until this pin is pulled low. Once it is driven to low logic, the device will respond to the default I2C 8-bit address (0x1E). A single I2C write to the FPC402 will reassign a new I2C address, and once this is done, the FPC402 will drive low logic with the CTRL4 pin (ADDR_DONE_N) which allows the next FPC402 in the daisy chain to be programmed using the default address. Until this address reassignment happens, the CTRL4 (ADDR_DONE_N) pin is high-Z.

This scheme allows each FPC402 to take a unique I2C address without any contention on the bus. The addresses may be programmed in any order except for the default 8-bit address (0x1E) which must be assigned to the last device in the daisy chain, or else two FPC402s will respond to 0x1E and bus contention will occur. The state of the CTRL3 (SET_ADDR_N) pin does not matter after the address is reprogrammed (this pin is then used to transfer the LED clock for blinking synchronization). Once the new address is programmed, it becomes fixed and may no longer be changed by a new register write. Only power cycling the device or toggling the EN pin will restore the device to the default reprogrammable address.

The I2C address space for FPC402 applications is designed such that each FPC402, each port being controlled, and each logical device address within each port is accessible to the host controller through a unique I2C address. All FPC402 devices will also respond to 8-bit I2C address 0x02. This allows the host controller to broadcast write to all FPC402 devices simultaneously. For a system with up to 14 FPC402 devices on a single I2C bus, the full 8-bit I2C address map is shown in Table 8-6.

The timing specification for an I2C transaction is described in Figure 8-5.

Figure 8-5 I2C Timing Diagram