ZHCSLX3C June 2017 – September 2020 FPC402
PRODUCTION DATA
For this design example, the following guidelines outlined in Table 9-1 apply.
| DESIGN PARAMETER | REQUIREMENT |
|---|---|
| FPC402 physical placement | The FPC402 package is small enough to fit underneath an SFP or QSFP cage, on the opposite side of the board. For SFP applications, such a placement leaves 4.6 mm of air gap between the FPC402 package edge and the SFP pressfit pins (assuming 14.25 mm pin-to-pin spacing for a stacked SFP cage). For QSFP applications, such a placement leaves 7.2 mm of air gap between the FPC402 package edge and the QSFP pressfit pins (assuming 19.5 mm pin-to-pin spacing for a stacked QSFP cage). |
| LED implementation | The FPC402 is designed to drive active-low LEDs which have their anode connected to the port-side 3.3 V supply. Refer to Section 8.3.2. |
| Port-side I2C SDA and SCL pullups | As per the SFF-8431 and SFF-8436 specification, the port-side (downstream) SCL and SDA nets must be pulled up to 3.3 V using resistors in the 4.7-kΩ to 10-kΩ range. |
| SFP Rate Select, RS0 and RS1 | The SFP module provides two inputs RS0 and RS1 that can optionally be used for rate selection. RS0 controls the receive path signaling rate capability, and RS1 controls the transmit path signaling rate capability. In the vast majority of applications, the receive and transmit rates will coincide, and RS0 and RS1 can be controlled by the same pin on the FPC402: OUT_B. For applications where RS0 and RS1 must be controlled independently, the GPIO[3:0] pins can be used in conjunction with OUT_B[3:0] to control both RS0 and RS1. |
| QSFP ModSelL | QSFP provides a mechanism to enable or disable the port’s I2C interface. Because the FPC402 has a separate I2C master to communicate with each port, the ModSelL input for every QSFP can be connected to GND, thereby permanently enabling each QSFP port’s I2C bus. |
| SFP/QSFP port power supply de-coupling | Follow the SFF-8431 and SFF-8436 recommendations for power supply de-coupling. |