The FPC402 has the ability to schedule a write operation on one or more downstream modules simultaneously by writing to local FPC402 registers. This operation, known as a scheduled write, allows for quicker writing by using the faster host-side I2C rate. The host-side I2C bus is not held while the write occurs in the downstream I2C. This command may be broadcasted to all FPC402s to write to any combination of ports concurrently. The downstream device address targeted by the scheduled write is configured between downstream device 0 and device 1, and both of these device addresses are fully configurable to any valid I2C address. By default, these addresses are 0xA0 and 0xA2, respectively.

Scheduled writes can be directed to an individual port (port scheduled write) or to a group of two or more ports simultaneously (common scheduled write). The status of the port scheduled write or common scheduled write may be checked in a local FPC402 register. This register will reflect if the operation completed successfully, or if it was NACKed by the downstream module. The on-going scheduled write command must be completed before the scheduled write settings for the target port are modified, or before a new command on the same port is issued.

Scheduled write operations have a higher priority than periodic prefetch operations. This means that if a schedule write is sent while a periodic prefetch is on-going, the periodic prefetch is stopped at the next byte boundary and the scheduled write is executed. The periodic prefetch resumes on the next period. Note that it will begin reading at the start of the prefetch range rather than where the scheduled write occurred.

Click here to request access to the FPC401 Programmer's Guide (SNLU221) for more details on how to configure scheduled write.