The FPC402 can be configured to prefetch data from each module of the downstream port. The prefetched data is stored locally in the memory of the device, allowing any downstream read operations in the prefetch range to be directly read from the FPC402 rather than waiting for the FPC402 to read from the downstream device through I2C. The FPC402 can prefetch data from the ports on a one-time basis, a regular basis (periodic prefetch), or upon the occurrence of certain events (interrupt-driven prefetch).

For periodic prefetching, the period is configured in steps of 5 ms from 0 to 1.275 s, where 0 is a one-time prefetch. The prefetched range is determined by two settings, the prefetch length and the prefetch offset address. The FPC402 will prefetch beginning at the offset address for a length of bytes between 1 and 32. The target device is configured between downstream device 0 and device 1, and both of these device addresses are fully configurable to any valid I2C address. By default, these addresses are 0xA0 and 0xA2 respectively. Once configured, the start bit is set to begin periodic prefetching and the stop bit is set to stop prefetching. After a prefetch is completed, the gate bit is set to 0, and any attempted read operation in the prefetched range will return data from the FPC402's memory containing the last prefetched data. To modify the prefetched range or to stop the FPC402 from returning the data from memory, the gate bit must be reset to 1. If the FPC402 receives a NACK during a prefetch attempt, the gate bit will automatically be reset. Each port has its own gate bit and separate memory and settings.

For interrupt-driven prefetch, the interrupt event can be configured for either the rising- or falling-edge of one of the IN_[A,B,C] input signals of a port. The prefetch range and target device address is configured similarly but independently of the periodic prefetch settings. Interrupt-driven prefetch also has a gate bit and memory independent of the periodic prefetch. Once an interrupt-driven prefetch occurs successfully, an interrupt is triggered on the HOST_INT_N pin and the aggregated interrupt flag for that port will be set. For the interrupt to be cleared and for another interrupt prefetch to occur, it must be re-armed with a register write. If the prefetch attempt is NACK'd, the gate bit will not be set, the interrupt will not be generated, and the interrupt-driven prefetch does not need to be re-armed. Note that the prefetched data from the interrupt-driven prefetch has precedence over the data from a periodic prefetch if they have overlapping prefetch ranges. The FPC402 will return data from the interrupt-driven prefetch even if the periodic prefetch data is more recent. When an interrupt-driven prefetch occurs, TI recommends correcting this immediately by reading the prefetched data and re-arming it.

Click here to request access to the FPC401 Programmer's Guide (SNLU221) for more details on how to configure data prefetch.