ZHCSLX3C June 2017 – September 2020 FPC402
PRODUCTION DATA
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| CAPL | 32 | O | Connect a single 2.2-µF capacitor to GND. |
| CTRL1 | 23 | I/O | Host-side control interface. These pins are used to implement I2C or SPI depending on the PROTOCOL_SEL pin configuration. I2C mode (PROTOCOL_SEL = Float or High): CTRL1: SCL – I2C Clock input / open-drain output CTRL2: SDA – I2C Data input / open-drain output CTRL3: SET_ADDR_N – input, address assignment enable. Also used to receive external LED clock. CTRL4: ADDR_DONE_N – output, address assignment complete. Also used to transmit LED clock. SPI mode (PROTOCOL_SEL = GND): CTRL1: SCK – Serial clock input CTRL2: SS_N – Active-low slave select input CTRL3: MOSI – Master output or slave input CTRL4: MISO – Master input or slave output |
| CTRL2 | 24 | I/O | |
| CTRL3 | 28 | I, Weak internal pullup | |
| CTRL4 | 21 | O | |
| EN | 22 | I, Weak internal pullup | Device enable. When EN = 0, the FPC402 is in a power-down state and does not respond to the host-side control bus, nor does it perform port-side I2C accesses. When EN=VDD2 or Float, the FPC402 is fully enabled and will respond to the host-side control bus provided VDD1 and VDD2 power has been stable for at least TPOR. VIH for this pin is referenced to VDD2.
The minimum required assert and deassert time is 12.5 µs. |
| GPIO[0] | 42 | I/O | General-purpose I/O. Output high voltage (VOH) and input high voltage (VIH) are based on VDD1. Configured as input (high-Z) by default. |
| GPIO[1] | 53 | ||
| GPIO[2] | 8 | ||
| GPIO[3] | 19 | ||
| GND | 27, DAP | Power | Ground reference. The GND pins must be connected through a low-resistance path to the board GND plane. |
| HOST_INT_N | 25 | O, Open-Drain | Open-drain 3.3-V tolerant active-low interrupt output. It asserts low to interrupt the host. The events which trigger an interrupt are programmable through registers. This pin can be connected in a wired-OR fashion with other FPC402s’ interrupt pins. A single pullup resistor to VDD1 or VDD2 in the 2-kΩ to 5-kΩ range is adequate for the entire net. |
| IN_A[0] | 41 | I, Weak internal pullup | Low-speed port status input A. Example usage: SFP: Mod_ABS[3:0] QSFP: ModPrsL[3:0] |
| IN_A[1] | 50 | ||
| IN_A[2] | 55 | ||
| IN_A[3] | 10 | ||
| IN_B[0] | 39 | I, Weak internal pullup | Low-speed port status input B. Example usage: SFP: Tx_Fault[3:0] QSFP: IntL[3:0] |
| IN_B[1] | 47 | ||
| IN_B[2] | 1 | ||
| IN_B[3] | 12 | ||
| IN_C[0] | 37 | I, Weak internal pullup | Low-speed port status input C. Example usage: SFP: Rx_LOS[3:0] QSFP: N/A |
| IN_C[1] | 46 | ||
| IN_C[2] | 3 | ||
| IN_C[3] | 14 | ||
| MOD_SCL[0] | 36 | I/O, Open-Drain | I2C clock open-drain output to the module. External 2-kΩ to 5-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant. |
| MOD_SCL[1] | 49 | ||
| MOD_SCL[2] | 4 | ||
| MOD_SCL[3] | 15 | ||
| MOD_SDA[0] | 35 | I/O, Open-Drain | I2C data input or open-drain output to the module. External 2-kΩ to 5-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant. |
| MOD_SDA[1] | 48 | ||
| MOD_SDA[2] | 5 | ||
| MOD_SDA[3] | 16 | ||
| OUT_A[0] | 40 | O | Low-speed port control output A. OUT_A is disabled by default (high-Z) and when enabled drives high logic unless reprogrammed. A 10-kΩ pullup or pulldown resistor is recommended to set a default logic value before this output is enabled. See Section 8.3.3 for more details. Example usage: SFP: Tx_Disable[3:0] QSFP: ResetL[3:0] |
| OUT_A[1] | 44 | ||
| OUT_A[2] | 56 | ||
| OUT_A[3] | 11 | ||
| OUT_B[0] | 38 | O | Low-speed port control output B. Output is disabled by default (high-Z) and when enabled drives low logic unless reprogrammed. A 10-kΩ pullup or pulldown resistor is recommended to set a default logic value before this output is enabled. See Section 8.3.3 for more details. Example usage: SFP: RS[3:0] QSFP: LPMode[3:0] |
| OUT_B[1] | 45 | ||
| OUT_B[2] | 2 | ||
| OUT_B[3] | 13 | ||
| OUT_C[0] | 34 | O | Low-speed port control output C. Can be used to drive port status LED. Special LED driving features are available on this output. This output is enabled and high logic by default at power up. See Section 8.3.2 for more details. Example usage: SFP: LED_GRN[3:0] QSFP: LED_GRN[3:0] This pin requires a series resistor with a value of at least 33 Ω. The LED current-limiting resistor can serve for this purpose. |
| OUT_C[1] | 51 | ||
| OUT_C[2] | 6 | ||
| OUT_C[3] | 17 | ||
| OUT_D[0] | 33 | O | Low-speed port control output D. Can be used to drive port status LED. Special LED driving features are available on this output. This output is enabled and high logic by default at power up. See Section 8.3.2 for more details. Example usage: SFP: LED_YLW[3:0] QSFP: N/A This pin requires a series resistor with a value of at least 33 Ω. The LED current-limiting resistor can serve for this purpose. |
| OUT_D[1] | 52 | ||
| OUT_D[2] | 7 | ||
| OUT_D[3] | 18 | ||
| PROTOCOL_SEL | 31 | I, Weak internal pullup | Used to select between I2C and SPI host-side control interface. Float or High: Inter-IC Control (I2C) GND: Serial Peripheral Interface (SPI) |
| SPI_LED_SYNC | 30 | I/O | LED clock synchronization pin for SPI mode only. When using SPI as the host-side control interface (PROTOCOL_SEL=GND), connect all FPC402 SPI_LED_CLK pins together. This ensures LED synchronization across all FPC402 devices. When using I2C as the host-side control interface, this pin can be floating. LED synchronization is ensured by other means in I2C mode. |
| TEST_N | 29 | I, Weak internal pullup | TI test mode. Float or High: Normal operation GND: TI Test Mode |
| VDD1 | 9, 43, 54 | Power | Main power supply, VDD1 = 3.3 V ± 5%. TI recommends connecting at least one 1-µF and one 0.1-µF decoupling capacitors per VDD1 pin as close to the pin as possible. |
| VDD2 | 20, 26 | Power | Power supply for host-side interface I/Os (CTRL[4:1]). VDD2 can be 1.8 V to 3.3 V ± 5%. If the host-side interface operates at 3.3 V, then VDD1 and VDD2 can be connected to the same 3.3-V ± 5% supply. TI recommends connecting at least one 1-µF and one 0.1-µF decoupling capacitors per VDD2 pin as close to the pin as possible. |