ZHCSE00E may   2014  – december 2020 HD3SS215

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1.     Pin Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-892340A8-A891-4B90-B8E2-B582AB533890/SLAS9018663 #GUID-892340A8-A891-4B90-B8E2-B582AB533890/SLAS9012713
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics, Device Parameters #GUID-222D29AA-746D-4606-8967-F0F2E648EFF8/SLAS9019128
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Speed Switching
      2. 8.3.2 HPD, AUX, and DDC Switching
      3. 8.3.3 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Switch Control Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 DisplayPort and Dual Mode Adapter with Two Sources
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 HDMI Application with Two Sinks
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 36
      4. 9.2.4 HDMI 2:1 Sink Application Using the RTQ Package
  11.   Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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10.2 Layout Example

An example layout for the HD3SS215 shows the device implemented on a 4-layer board. The layout figures follow the DisplayPort application schematic above. The top layer layout view shows the signal routing for two sources and one sink. The bottom layer layout view shows the remaining signal routing and a copper pour implemented for the decoupling capacitors.

GUID-00C447B3-0EB0-4FA3-A558-8CA3F8374ADA-low.gifFigure 10-1 Top Layer Layout View
GUID-A5601975-CB96-4617-8A49-C54F00E7F74A-low.gifFigure 10-2 Bottom Layer Layout View
GUID-8F8C5502-A28D-4D7D-AD3D-19372B9E15DB-low.gifFigure 10-3 RTQ Layout for 2:1 HDMI Sink Application
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