ZHCSE00E may   2014  – december 2020 HD3SS215

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-892340A8-A891-4B90-B8E2-B582AB533890/SLAS9018663 #GUID-892340A8-A891-4B90-B8E2-B582AB533890/SLAS9012713
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics, Device Parameters #GUID-222D29AA-746D-4606-8967-F0F2E648EFF8/SLAS9019128
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Speed Switching
      2. 8.3.2 HPD, AUX, and DDC Switching
      3. 8.3.3 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Switch Control Modes
  10. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 DisplayPort and Dual Mode Adapter with Two Sources
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 HDMI Application with Two Sinks
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 36
      4. 9.2.4 HDMI 2:1 Sink Application Using the RTQ Package
  11.   Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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Layout Guidelines

  • The ESD and EMI protection devices (if used) should be placed as close as possible to the connector.
  • Place voltage regulators as far away as possible from the high-speed differential pairs.
  • It is recommended that small decoupling capacitors for the HD3SS215 power rail be placed close to the device.
  • The high-speed differential signal traces should be routed on the top layer to avoid the use of vias and allow clean interconnects to the mux.
  • The high speed differential signal traces should be routed parallel to each other as much as possible. It is recommended the traces be symmetrical.
  • In order to control impedance for transmission lines, a solid ground plane should be placed next to the high-speed signal layer. This also provides an excellent low-inductance path for the return current flow.
  • The power plane should be placed next to the ground plane to create additional high-frequency bypass capacitance.
  • Adding test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes stubs on the differential pair.
  • Avoid 90 degree turns in traces. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥135 degrees. This will minimize any length mismatch caused by the bends and therefore minimize the impact bends have on EMI.