ZHCSE00E may   2014  – december 2020 HD3SS215

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1.     Pin Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-892340A8-A891-4B90-B8E2-B582AB533890/SLAS9018663 #GUID-892340A8-A891-4B90-B8E2-B582AB533890/SLAS9012713
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics, Device Parameters #GUID-222D29AA-746D-4606-8967-F0F2E648EFF8/SLAS9019128
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Speed Switching
      2. 8.3.2 HPD, AUX, and DDC Switching
      3. 8.3.3 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Switch Control Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 DisplayPort and Dual Mode Adapter with Two Sources
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 HDMI Application with Two Sinks
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 36
      4. 9.2.4 HDMI 2:1 Sink Application Using the RTQ Package
  11.   Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-A09CAC2B-30C7-40C9-BA5E-F38CD102C266-low.gifFigure 6-1 50-Pin µBGAZXH Package(Top View)
GUID-A1705872-9823-4457-8C69-A73079E42FF3-low.gifFigure 6-2 56-Pin QFNRTQ Package(Top View)
Table 6-1 Pin Functions
PIN I/O DESCRIPTION(1)
NAME NO.
ZXH RTQ
Dx_SEL A1 56 2 Level Control I High Speed Port Selection Control Pins
AUX_SEL C2 1 3 Level Control I AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
DA0(p) B4 54 I/O Port A, Channel 0, High Speed Positive Signal
DA0(n) A4 53 Port A, Channel 0, High Speed Negative Signal
DA1(p) B5 51 I/O Port A, Channel 1, High Speed Positive Signal
DA1(n) A5 50 Port A, Channel 1, High Speed Negative Signal
DA2(p) B6 48 I/O Port A, Channel 2, High Speed Positive Signal
DA2(n) A6 47 Port A, Channel 2, High Speed Negative Signal
DA3(p) A8 45 I/O Port A, Channel 3, High Speed Positive Signal
DA3(n) A9 44 Port A, Channel 3, High Speed Negative Signal
DB0(p) B8 41 I/O Port B, Channel 0, High Speed Positive Signal
DB0(n) B9 40 Port B, Channel 0, High Speed Negative Signal
DB1(p) D8 38 I/O Port B, Channel 1, High Speed Positive Signal
DB1(n) D9 37 Port B, Channel 1, High Speed Negative Signal
DB2(p) E8 35 I/O Port B, Channel 2, High Speed Positive Signal
DB2(n) E9 34 Port B, Channel 2, High Speed Negative Signal
DB3(p) F8 32 I/O Port B, Channel 3, High Speed Positive Signal
DB3(n) F9 31 Port B, Channel 3, High Speed Negative Signal
DC0(p) B2 2 I/O Port C, Channel 0, High Speed Positive Signal
DC0(n) B1 3 Port C, Channel 0, High Speed Negative Signal
DC1(p) D2 5 I/O Port C, Channel 1, High Speed Positive Signal
DC1(n) D1 6 Port C, Channel 1, High Speed Negative Signal
DC2(p) E2 8 I/O Port C, Channel 2, High Speed Positive Signal
DC2(n) E1 9 Port C, Channel 2, High Speed Negative Signal
DC3(p) F2 11 I/O Port C, Channel 3, High Speed Positive Signal
DC3(n) F1 12 Port C, Channel 3, High Speed Negative Signal
AUXA(p) H9 30 I/O Port A AUX Positive Signal
AUXA(n) J9 29 Port A AUX Negative Signal
AUXB(p) H6 24 I/O Port B AUX Positive Signal
AUXB(n) J6 25 Port B AUX Negative Signal
AUXC(p) H2 13 I/O Port C AUX Positive Signal
AUXC(n) H1 14 Port C AUX Negative Signal
DDCCLK_A H8 27 I/O Port A DDC Clock Signal
DDCDAT_A J8 28 Port A DDC Data Signal
DDCCLK_B H5 22 I/O Port B DDC Clock Signal
DDCDAT_B J5 23 Port B DDC Data Signal
DDCCLK_C J3 18 I/O Port C DDC Clock Signal
DDCDAT_C J7 26 Port C DDC Data Signal
HPDA/B/C J2, H3, J1 16, 17, 15 I/O Port A/B/C Hot Plug Detect
OE B7 43 I Output Enable:
OE = VIH: Normal Operation
OE = VIL: Standby Mode
VDD A2, J4 19, 55 Supply 3.3 V Positive power supply voltage
GND B3, C8, G2, G8 H4, H7 4, 7, 10, 33, 36, 39, 46, 49, 52 Supply Ground
NC 20, 21, 42 Not connected
Thermal Pad – – GND Supply Ground
(1) Only the high speed data DAz/DBz ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and switched out when the port is selected.
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