Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the plane.
Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines.
Route all differential pairs on the top or bottom
layer (microstrip traces) if possible or on the
same group of layers. Only use vias in the
breakout region of the device if vias are
necessary for routing. Avoid using vias in the
main region of the board at all cost. Use a ground
reference via next to signal via. Distance between
ground reference via and signal need to be
calculated to have similar impedance as
traces.
Make sure not all differential signals are routed
over a plane split. Changing signal layers is
preferable to crossing plane splits.
Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high frequency return current path.
Route differential traces over a continuous plane with no interruptions.
Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or any magnetic source.
Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep out distance where possible.
Place the decoupling caps next to each power
terminal on the HD3SS3411-Q1. Take care to minimize the stub length of the
trace connecting the capacitor to the power pin.
Avoid sharing vias between multiple decoupling caps.
Place vias as close as possible to the decoupling cap solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.