10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

• Connect low-ESR, 1-µF and 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. Connecting bypass capacitors only from V+ to ground is acceptable in single-supply applications. Noise can propagate into analog circuitry through the power pins of this device. The bypass capacitors reduce the coupled noise by providing low-impedance pathways to ground.
• Connect the device REF pins to a low-impedance, low-noise, system reference point (such as an analog ground or the VMID(OUT) pin) with the shortest trace possible.
• Place the external components as close to the device as possible, as shown in Figure 62 and Figure 63.
• Use ground pours and planes to shield input signal traces and minimize additional noise introduced into the signal path.
• Keep the length of input traces equal and as short as possible. Route the input traces as a differential pair with as minimal spacing between them as possible.