ZHCSFN8G May   2004  – January 2015 INA193 , INA194 , INA195 , INA196 , INA197 , INA198

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic Connection
      2. 8.3.2 Selecting RS
      3. 8.3.3 Inside the INA193-INA198
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Filtering
      2. 8.4.2 Accuracy Variations as a Result of VSENSE and Common-Mode Voltage
        1. 8.4.2.1 Normal Case 1: VSENSE ≥ 20mv, VCM ≥ VS
        2. 8.4.2.2 Normal Case 2: VSENSE ≥ 20mv, VCM < VS
        3. 8.4.2.3 Low VSENSE Case 1: VSENSE < 20mV, −16v ≤ VCM < 0; and Low VSENSE Case 3: VSENSE < 20mV, VS < VCM ≤ 80V
        4. 8.4.2.4 Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
      3. 8.4.3 Shutdown
      4. 8.4.4 Transient Protection
      5. 8.4.5 Output Voltage Range
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 RFI and EMI
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply Voltage 18 V
Analog Inputs, VIN+, VIN− –18 18 V
Differential (VIN+) – (VIN−) –18 18 V
Common-Mode(2) –16 80 V
Analog Output, Out(2) GND – 0.3 (V+) + 0.3 V
Input Current Into Any Pin(2) 5 mA
Operating Temperature –55 150 °C
Junction Temperature 150 °C
Storage temperature, Tstg –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input voltage at any pin may exceed the voltage shown if the current at that pin is limited to 5mA.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCM Common-mode input voltage 12 V
V+ Operating supply voltage 12 V
TA Operating free-air temperature -40 125 ºC

Thermal Information

THERMAL METRIC(1) INA19x UNIT
DBV (SOT-23)
5 PINS
RθJA Junction-to-ambient thermal resistance 221.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 144.7
RθJB Junction-to-board thermal resistance 49.7
ψJT Junction-to-top characterization parameter 26.1
ψJB Junction-to-board characterization parameter 49.0
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

All specifications at TA = 25°C, VS = 12 V, VIN+ = 12 V, and VSENSE = 100 mV, unless otherwise noted.
PARAMETER TEST CONDITIONS TA = 25°C TA = −40°C to +125°C UNIT
MIN TYP MAX MIN TYP MAX
INPUT
VSENSE Full-Scale Input Voltage VSENSE = VIN+ − VIN− 0.15 (VS – 0.2)/Gain –16 V
VCM Common-Mode Input Range 80 –16 V
CMR Common-Mode Rejection VIN+ = −16 V to 80 V 80 94 dB
Common-Mode Rejection, Over Temperature VIN+ = 12 V to 80 V 100 120 dB
VOS Offset Voltage, RTI ±0.5 2 mV
Offset Voltage, RTI Over Temperature 0.5 3 mV
dVOS/dT Offset Voltage, RTI vs Temperature 2.5 μV/°C
PSR Offset Voltage, RTI vs Power Supply VS = 2.7 V to 18 V, VIN+ = 18 V 5 100 μV/V
IB Input Bias Current, VIN− pin ±8 ±16 μA
OUTPUT (VSENSE ≥ 20mV)
G Gain INA193, INA196 20 V/V
INA194, INA197 50 V/V
INA195, INA198 100 V/V
Gain Error VSENSE = 20 mV to 100 mV,
TA = 25°C
±0.2% ±1%
Gain Error Over Temperature VSENSE = 20 mV to 100 mV ±2
Total Output Error(1) VSENSE = 100 mV ±0.75% ±2.2%
Total Output Error Over Temperature ±1% ±3%
Nonlinearity Error VSENSE = 20 mV to 100 mV ±0.002% ±0.1%
RO Output Impedance 1.5 Ω
Maximum Capacitive Load No Sustained Oscillation 10 nF
Output(4) All Devices −16 V ≤ VCM < 0 V, VSENSE < 20 mV 300 mV
VS < VCM ≤ 80 V, VSENSE < 20 mV 300
INA193, INA196 0 V ≤ VCM ≤ VS,
VS = 5 V,
VSENSE < 20 mV
0.4 V
INA194, INA197 1 V
INA195, INA198 2 V
VOLTAGE OUTPUT(2) (RL = 100 kΩ to GND)
Swing to V+ Power-Supply Rail (V+) – 0.1 (V+) – 0.2 V
Swing to GND(3) (VGND) + 3 (VGND) + 50 mV
FREQUENCY RESPONSE
BW Bandwidth INA193, INA196 CLOAD = 5 pF 500 kHz
INA194, INA197 300 kHz
INA195, INA198 200 kHz
Phase Margin CLOAD < 10 nF 40
SR Slew Rate 1 V/μs
tS Settling Time (1%) VSENSE = 10 mV to 100 mVPP,
CLOAD = 5 pF
2 μs
NOISE, RTI
Voltage Noise Density 40 nV/√Hz
POWER SUPPLY
VS Operating Range 2.7 18 V
IQ Quiescent Current VOUT = 2 V 700 900 μA
Quiescent Current Over Temperature VSENSE = 0 mV 370 950 μA
TEMPERATURE RANGE
Specified Temperature Range –40 125 °C
Operating Temperature Range –55 150 °C
Storage Temperature Range –65 150 °C
θJA Thermal Resistance, SOT23 200 °C/W
Total output error includes effects of gain error and VOS.
See Typical Characteristic curve Output Swing vs Output Current, Figure 7.
Specified by design.
For details on this region of operation, see the Accuracy Variations as a Result of VSENSE and Common-Mode Voltage section.

Typical Characteristics

All specifications at TA = 25°C, VS = 12 V, and VIN+ = 12 V, and VSENSE = 100 mV, unless otherwise noted.
INA193 INA194 INA195 INA196 INA197 INA198 tc_g-frq_cl_bos307.gif
Figure 1. Gain vs Frequency
INA193 INA194 INA195 INA196 INA197 INA198 tc_g_plot_bos307.gif
Figure 3. Gain Plot
INA193 INA194 INA195 INA196 INA197 INA198 tc_oerr-vs_bos307.gif
Figure 5. Output Error vs VSENSE
INA193 INA194 INA195 INA196 INA197 INA198 tc_voswing-io_bos307.gif
Figure 7. Positive Output Voltage Swing vs Output Current
INA193 INA194 INA195 INA196 INA197 INA198 D101_SBOS307.gif
Figure 9. Input Bias Current vs Common Mode Voltage
Vs=5 V
INA193 INA194 INA195 INA196 INA197 INA198 tc_iq-vcm_bos307.gif
Figure 11. Quiescent Current vs Common-Mode Voltage
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_10-20_g20_bos307.gif
Figure 13. Step Response
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_90-100_g20_bos307.gif
Figure 15. Step Response
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_10-100_g50_bos307.gif
Figure 17. Step Response
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_10-100_g100_bos307.gif
Figure 19. Step Response
INA193 INA194 INA195 INA196 INA197 INA198 tc_g-frq_bos307.gif
Figure 2. Gain vs Frequency
INA193 INA194 INA195 INA196 INA197 INA198 tc_cmrr_psrr-frq_bos307.gif
Figure 4. Common-Mode and Power-Supply Rejection vs Frequency
INA193 INA194 INA195 INA196 INA197 INA198 tc_oerr-vcm_bos307.gif
Figure 6. Output Error vs Common-Mode Voltage
INA193 INA194 INA195 INA196 INA197 INA198 tc_iq-vo_bos307.gif
Figure 8. Quiescent Current vs Output Voltage
INA193 INA194 INA195 INA196 INA197 INA198 D102_SBOS307.gif
Figure 10. Input Bias Current vs Common Mode Voltage Vs=12 V
INA193 INA194 INA195 INA196 INA197 INA198 tc_io_shrt-vs_bos307.gif
Figure 12. Output Short-Circuit Current vs Supply Voltage
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_10-100_g20_bos307.gif
Figure 14. Step Response
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_10-20_g50_bos307.gif
Figure 16. Step Response
INA193 INA194 INA195 INA196 INA197 INA198 tc_step_90-100_g50_bos307.gif
Figure 18. Step Response