ZHCSFN6F March   2007  – June 2021 INA203 , INA204 , INA205

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Current-Shunt Monitor
    6. 6.6 Electrical Characteristics: Comparator
    7. 6.7 Electrical Characteristics: Reference
    8. 6.8 Electrical Characteristics: General
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Basic Connections
      2. 7.3.2 Selecting RSHUNT
      3. 7.3.3 Comparator
      4. 7.3.4 Comparator Delay (14-Pin Version Only)
      5. 7.3.5 Comparator Maximum Input Voltage Range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Filtering
      2. 7.4.2 Accuracy Variations as a Result Of VSENSE and Common-Mode Voltage
        1. 7.4.2.1 Normal Case 1: VSENSE ≥ 20 mV, VCM ≥ VS
        2. 7.4.2.2 Normal Case 2: VSENSE ≥ 20 mV, VCM < VS
        3. 7.4.2.3 Low VSENSE Case 1
        4. 7.4.2.4 Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
      3. 7.4.3 Transient Protection
      4. 7.4.4 Output Voltage Range
      5. 7.4.5 Reference
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|14
  • DGS|10
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Electrical Characteristics: Comparator

At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1 OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Offset Voltage Comparator Common-Mode Voltage = Threshold Voltage 2 mV
Offset Voltage Drift, Comparator 1 TA = –40°C to 125°C ±2 μV/°C
Offset Voltage Drift, Comparator 2 TA = –40°C to 125°C 5.4 μV/°C
Threshold TA = 25°C 590 608 620 mV
Threshold over Temperature TA = –40°C to 125°C 586 625 mV
Hysteresis (1), CMP1 TA = –40°C to 85°C –8 mV
Hysteresis (1), CMP2 TA = –40°C to 85°C 8 mV
INPUT BIAS CURRENT (2)
CMP1 IN+, CMP2 IN+ 0.005 10 nA
CMP1 IN+, CMP2 IN+ vs. Temperature TA = –40°C to 125°C 15 nA
INPUT IMPEDANCE
Pins 3 and 6 (14-pin packages only) 10 kΩ
INPUT RANGE
CMP1 IN+ and CMP2 IN+ 0 V to VS – 1.5 V V
Pins 3 and 6 (14-pin packages only) (3) 0 V to VS – 1.5 V V
OUTPUT
Large-Signal Differential Voltage Gain CMP VOUT 1 V to 4 V, RL ≥ 15 kΩ Connected to 5 V 200 V/mV
High-Level Output Current VID = 0.4 V, VOH = VS 0.0001 1 μA
Low-Level Output Voltage VID = –0.6 V, IOL = 2.35 mA 220 300 mV
RESPONSE TIME (4)
Comparator 1 RL to 5 V, CL = 15 pF, 100-mV Input Step with 5-mV Overdrive 1.3 μs
Comparator 2 RL to 5 V, CL = 15 pF, 100-mV Input Step with 5-mV Overdrive, CDELAY Pin Open 1.3 μs
RESET
RESET Threshold (5) 1.1 V
Logic Input Impedance 2 MΩ
Minimum RESET Pulse Width 1.5 μs
RESET Propagation Delay 3 μs
Comparator 2 Delay Equation (6) CDELAY = tD/5 μF
tD Comparator 2 Delay CDELAY = 0.1 μF 0.5 s
(1) Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the noninverting input of the comparator; refer to Figure 6-1.
(2) Specified by design; not production tested.
(3) See the Section 7.3.5 section in the Section 8.
(4) The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
(5) The CMP1 RESET input has an internal 2-MΩ (typical) pulldown. Leaving the CMP1 RESET open results in a LOW state, with transparent comparator operation.
(6) The Comparator 2 delay applies to both rising and falling edges of the comparator output.
GUID-8CE16FD9-085B-4F8C-AD77-692E6F5AB91B-low.gifFigure 6-1 Comparator Hysteresis
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